System-level verification method and system of chip and related device

Abstract

The invention provides a system-level verification method of a chip. The system-level verification method comprises the steps of receiving a verification request; confirming a module path and a module name of a to-be-verified module according to the verification request; wherein the to-be-verified module comprises a to-be-rejected module and a to-be-replaced module; analyzing the to-be-verified module by utilizing a rejection script to execute a hollowing operation to obtain a port signal, and generating a hollowing file in combination with the module path and the module name; assigning a value to a port signal in the hollowed-out file to obtain a hollowed-out module; and replacing the to-be-verified module with the hollow module, and adding the to-be-verified module to a simulation script for system-level verification. The verification influence on other modules can be reduced when the to-be-verified module is not completed, and the verification period is shortened. The invention further provides a system-level verification system of the chip, a computer readable storage medium and electronic equipment, which have the above beneficial effects.

Description

technical field [0001] The present application relates to the field of chip verification, in particular to a chip system-level verification method, system and related devices. Background technique [0002] In the entire chip development and design process, functional verification has become the largest and most time-consuming bottleneck. At present, more and more chip design companies adopt the system-on-a-chip (SoC) design strategy of self-developing core functional modules and outsourcing general modules, but it brings severe challenges to the system-level functional verification of chips. challenge. System-level verification mainly confirms that the chip architecture meets the given functional / performance requirements, by converting user requirements into functional / performance requirements, and realizing behavior / functional design, and then mapping to the corresponding architecture (design input, hard IP core , soft IP core, software / hardware division, performance anal...

AI Technical Summary

Problems solved by technology

[0004] However, if each system-level verification needs to rebuild the verification environment and write verification codes, it will consume huge time and labor costs.

In addition, during the test process, it often happens that some of the modules have been purchased or developed, while other interconnected modules cannot be delivered in time, which affects the collaborative function verification

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