Multistage cache consistency pipeline processing method and device

A processing method and technology of a processing device, applied in the computer field, can solve problems such as affecting system performance, large chip resource occupation, poor timing, etc., and achieve the effects of improving processing efficiency, improving performance, and improving timing.

Inactive Publication Date: 2014-09-17
INSPUR BEIJING ELECTRONICS INFORMATION IND
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  • Abstract
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Problems solved by technology

In addition, there may also be resource and address conflicts in the process of Cache consistency maintenance, so there will be a large amount of chip resource usage and poor timing
If there are requests to the same address in a continuous period of

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  • Multistage cache consistency pipeline processing method and device
  • Multistage cache consistency pipeline processing method and device

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Embodiment Construction

[0022] The present invention will be described in detail below in conjunction with specific embodiments shown in the accompanying drawings.

[0023] The method and device for Cache consistent multi-stage pipeline processing of the present invention are applicable to the scene where there is a certain dependence relationship between the pipeline information of the previous stage and the pipeline information processing of the subsequent stage, and this dependence relationship becomes the key path of the system. In the present invention, the pipeline processing mechanism of multi-stage pipeline and same-address message blocking is mainly adopted to solve the problem caused by the conflict of same-address message in the Cache consistency process.

[0024] figure 1 It is a structural schematic diagram of the Cache consistency multi-stage pipeline processing device of the present invention, such as figure 1 As shown, it includes a pipeline scheduling module 11 , a pipeline processi...

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Abstract

The invention provides a multistage cache consistency pipeline processing method and device. The method comprises the steps that message information of currently-scheduled messages to be processed is obtained, wherein the message information comprises address information; whether the messages to be processed are effective messages is judged according to the message information, and if the messages to be processed are judged to be the effective messages, according to the address information in the message information, whether the effective messages which are unprocessed and have the same addresses as the messages to be processed exist is judged; if it is judged that the effective messages which are unprocessed and have the same addresses as the messages to be processed exist, the messages to be processed are blocked; if it is judged that the effective messages which are unprocessed and have the same addresses as the messages to be processed do not exist, cache consistency processing is carried out on the messages to be processed; by blocking the messages, to be processed, of the same addresses, when the cache consistency processing is carried out, resources are saved; moreover, timing sequence is good, and therefore the performance of a system is promoted.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a method and device for processing a consistent multi-stage pipeline of a cache memory (Cache). Background technique [0002] During the development of computer technology, the access speed of the main memory has always been much slower than the operation speed of the central processing unit (CPU, Central Processing Unit), so that the high-speed processing capability of the central processing unit cannot be fully utilized. Cache is a high-speed small-capacity memory between the CPU and the main memory in the hierarchical structure of the computer storage system. Its capacity is generally only a few hundredths of the main memory, but its access speed can match that of the CPU. . According to the principle of program locality, there is a high probability that those units adjacent to a unit of main memory being used will be used. Therefore, when the CPU accesses a certain unit o...

Claims

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Application Information

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IPC IPC(8): G06F9/38
Inventor 刘强陈继承周恒钊胡雷钧
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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