Cache consistency test method

Abstract

The present invention provides a cache consistency test method. The method comprises the steps of: a master process applying for a shared space; the master process creating a plurality of sub processes; dividing four shared space parts in the shared space; the master process arranging numbers of memory blocks accessed by a read operation and a write operation, so as to allow memory addresses accessed by the read operation and write operation not to overlap, and allow the plurality of sub processes to enter synchronous interfaces; after the plurality of sub processes are synchronized successfully, reading an arranged sequence, so as to allow the master process and the plurality of sub processes to perform read and write operations simultaneously; and after the master process and the plurality of sub processes finish read and write operations, each process using an exclusive OR operation to calculate the weight of a read space and a write space accessed by the process, and comparing the weight of the memory accessed by the read operation with the weight of the memory accessed by the write operation.

Description

technical field [0001] The invention relates to the technical field of cache consistency verification of multi-core processors, in particular to a cache consistency test method. Background technique [0002] The use of cache technology is to match the speed of the processor and the access speed of the memory. On most modern processors, almost all memory access needs to be performed through the cache. With the development of multi-processor, multi-core, and many-core technologies, the speed of processors is getting faster and faster, and the memory hierarchy is becoming more and more complex, and the problem of cache coherence (Cache coherence) becomes more and more prominent. Cache coherency refers to the mechanism by which shared resources held in cache maintain data consistency. [0003] With the increase of processor storage levels, data inconsistency may occur between adjacent levels and within the same level. This problem is particularly prominent in multi-core and man...

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a cache consistency test method for the above-mentioned defects in the prior art, which can solve the problems of many cache consistency scenarios and difficult traversal when multi-core processors run parallel programs. Automatic memory access mode generation system to generate parallel verification programs covering various memory access scenarios, and fully verify the cache consistency of the processor in the early stage of chip design and sample stage, so as to ensure the success rate of one-time chip release, thereby reducing chip Design costs, shorten the development cycle

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