Multiprocessor system and Cache consistency message transmission method

Abstract

The invention provides a multiprocessor system which accords with an AXI protocol. The system comprises at least two processor cores including a first-level cache, and at least two second-level caches, the processor cores are connected with the second-level caches by a bus; the bus comprises a read address channel, a read data channel, a write address channel, a write data channel and a write response channel; the lines in the channels are divided into regions according to the transmitted contents, and the channels comprise the regions which are defined according to the AXI protocol; wherein, the write address channel further comprises an AWDID region for identifying a target ID of the write address request, and an AWSTATE region for transmitting state information of a cache block in the first-level cache in write operation; the write data channel further comprises a WDID region for identifying the target ID of the write data request; the read address channel further comprises an ARDID region for identifying the target ID of the write address request and an ARCMD region for representing a read command; and the read data channel further comprises an RSTATE region for representing a read data response.

Description

technical field [0001] The invention relates to the field of microprocessor architecture, in particular to a multiprocessor system and a Cache consistency message transmission method. Background technique [0002] As semiconductor technology advances, processor designers can use more transistor resources to implement higher-performance chips. At the same time, the target workload is constantly changing, from scientific computing in the early days to the coexistence of personal desktop applications, server transaction processing, e-commerce applications and various embedded applications today. Under the double impetus of application requirements and the improvement of semiconductor technology level, a chip multi-processor structure (Chip Multi-Processor, CMP for short) with a higher degree of parallelism has emerged as the times require, and has become the latest development direction of the current high-performance processor architecture. Cache (high-speed cache, referred t...

AI Technical Summary

Problems solved by technology

[0005] Due to the lack of support for Cache coherent message transmission in existing bus standards, the application range of processors using such bus standards is limited

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