Method for building multi-processor node system with multiple cache consistency domains

A multi-processor, consistent technology, applied in memory systems, electrical digital data processing, instruments, etc., can solve problems such as system efficiency drop, performance loss, and topology complexity between nodes, so as to reduce system topology complexity and improve system performance effect

Active Publication Date: 2013-04-17
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

With so many node controllers, the scale of interconnection between nodes is very large, and the topology between nodes becomes more and more complex; the speed of cross-node access to remote memory is significantly deteriorated, which in turn leads to a rapid decline in system efficiency and a huge loss in performance

Method used

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  • Method for building multi-processor node system with multiple cache consistency domains
  • Method for building multi-processor node system with multiple cache consistency domains
  • Method for building multi-processor node system with multiple cache consistency domains

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Embodiment

[0043] A multi-processor system with multiple nodes, for each node, a unified logical cache coherence domain is built inside its node controller to completely contain multiple physical caches consisting of several processors and the node controller that are isolated from each other Consistency domain; and its nodes can be directly connected through the node controller or connected through the node router (NR) to form a single cache consistency domain between nodes;

[0044] In addition, the first-level node controller of the above-mentioned system can be connected to the second-level node controller, and a unified logical cache coherence domain is constructed inside the second-level node controller to completely contain the isolation between several first-level node controllers and the Multiple physical cache coherence domains composed of secondary node controllers; connected directly or through node routers (NRs) through their secondary node controllers to form a single cache ...

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Abstract

The invention provides a method for building a multi-processor node system with multiple cache consistency domains. In the system, a directory built in a node controller needs to include processor domain attribute information, and the information can be acquired by configuring cache consistency domain attributes of ports for connecting the node controller with processors. The node controller can support the multiple physical cache consistency domains in nodes. The method aims to decrease the number of node controllers in the multi-processor computer system, decrease the scale of interconnection of the nodes, reduce topological complexity of the nodes and improve system efficiency. Besides, the method can solve the problems that the number of processor interconnection ports and the number of supportable intra-domain processor IDs (identities) are extremely limited, and performance bottleneck is caused in building of a large-scale CC-NUMA (cache coherent non-uniform memory access) system.

Description

technical field [0001] The invention relates to the field of computer applications, in particular to a method for constructing a multi-processor node system with multiple cache coherency domains. Background technique [0002] For a multiprocessor system, its multiple processors share the system memory space. At present, the connection mode between multiprocessors has changed from bus connection to point-to-point connection, and the memory has also changed from being connected to an external bridge chip of the processor to being directly connected to the processor. Due to changes in memory mounting methods, the distribution of memory in the system also changes, resulting in non-uniform memory access in multiprocessor systems. Therefore, most current multiprocessor systems are NUMA (Non-Uniform Memory Access - non- Uniform Memory Access) architecture system. [0003] The NUMA architecture multiprocessor system has the following three important characteristics: [0004] 1. A...

Claims

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Application Information

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IPC IPC(8): G06F15/167G06F12/0817
CPCG06F12/082G06F12/0822G06F12/0826G06F15/17368G06F2212/1016G06F2212/1048G06F2212/2542G06F2212/622
Inventor 王恩东胡雷钧陈继承张东公维锋张峰
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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