145 results about "Processor sharing" patented technology

A method for controlling exclusive access to a resource shared by multiple processors in a data storage system includes providing a system lock procedure to permit a processor to obtain a lock on the shared resource preventing other processors from accessing the shared resource and providing a faked lock procedure to indicate to the system lock procedure that a processor has a lock on the shared resource where such a lock does not exist, and wherein the faked lock procedure prevents another processor from obtaining the lock on the shared resource, but does not prevent other processors from accessing the shared resource. A data storage system according to the invention includes a shared resource, a plurality of processors coupled to the shared resource through a communication channel, and a lock services procedure providing the system lock procedure and the faked lock procedure. In one embodiment, the shared resource is a cache and the system lock procedure permits a processor to lock the entire cache whereas the faked lock procedure is implemented by a processor seeking exclusive access of a cache slot.

A peripheral such as a printer is controlled to receive data from different data ports. A first port receives data formatted according to a first protocol. A second port receives data formatted according to a second protocol. A first processor is associated with the peripheral. A second processor is associated with the second port. A switch is adapted to receive (i) first data from the first port and (ii) second data from the second port after processing by the second processor. The switch is controlled in response to a command received via the second port to couple either the first data or second data to the first processor for use in controlling the peripheral. New firmware can be downloaded to the peripheral via the second port in response to the command. The command can be communicated to the first processor via a separate port at the first processor and a memory shared with the second processor.

Cache states for cache coherency protocols for a multiprocessor system are described. Some embodiments described include a multiprocessor computer system comprising a plurality of cache memories to store a plurality of cache lines and state information for each one of the cache lines. The state information comprises data representing a first state selected from the group consisting of a Shared-Update state, a Shared-Respond state and an Exclusive-Respond state. The multiprocessor computer system further comprises a plurality of processors with at least one cache memory associated with each one of the plurality of processors. The multiprocessor computer system further comprises a system memory shared by the plurality of processors, and at least one bus interconnecting the system memory with the plurality of cache memories and the multiple processors. In some embodiments, one or more of the states (a Shared-Update state, a Shared-Respond state or an Exclusive-Respond state) are implemented in conjunction with the states of the MESI protocol.

A multipath accessible semiconductor memory device provides an interfacing function between multiple processors which indirectly controls a flash memory. The multipath accessible semiconductor memory device comprises a shared memory area, an internal register and a control unit. The shared memory area is accessed by first and second processors through different ports and is allocated to a portion of a memory cell array. The internal register is located outside the memory cell array and is accessed by the first and second processors. The control unit provides storage of address map data associated with the flash memory outside the shared memory area so that the first processor indirectly accesses the flash memory by using the shared memory area and the internal register even when only the second processor is coupled to the flash memory. The control unit also controls a connection path between the shared memory area and one of the first and second processors. The processors share the flash memory and a multiprocessor system is provided that has a compact size, thereby substantially reducing the cost of memory utilized within the multiprocessor system.

Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors.

A system and method are provided to dedicate one or more processors in a multiprocessing system to performing encryption functions. When the system initializes, one of the synergistic processing unit (SPU) processors is configured to run in a secure mode wherein the local memory included with the dedicated SPU is not shared with the other processors. One or more encryption keys are stored in the local memory during initialization. During initialization, the SPUs receive nonvolatile data, such as the encryption keys, from nonvolatile register space. This information is made available to the SPU during initialization before the SPUs local storage might be mapped to a common memory map. In one embodiment, the mapping is performed by another processing unit (PU) that maps the shared SPUs' local storage to a common memory map.

The cache arrangement includes a cache that may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache. Associated with each processor is a unique extent increment used to determine a next location for that particular processor when attempting to locate an available slot.

The invention discloses a method for realizing a cache coherence protocol of a chip multiprocessor (CMP) system, and the method comprises the following steps: 1, cache is divided into a primary Cache and a secondary Cache, wherein the primary Cache is a private Cache of each processor in the processor system, and the secondary Cache is shared by the processors in the processor system; 2, each processor accesses the private primary Cache, and when the access fails, a failure request information slot is generated, sent to a request information ring, then transmitted to other processors by the request information ring to carry out intercepting; and 3, after a data provider intercepts the failure request, a data information slot is generated and sent to a data information ring, then transmitted to a requestor by the data information ring, finally, the requestor receives data blocks and then completes corresponding access operations. The method disclosed by the invention has the advantages of effectively improving the performance of the system, reducing the power consumption and bandwidth utilization, avoiding the occurrence of starvation, deadlock and livelock, and improving the stability of the system.

According to the present invention, methods and apparatus are provided to allow dynamic multiple cluster system configuration changes. In one example, processors in the multiple cluster system share a virtual address space. Mechanisms for dynamically introducing and removing processors, I/O resources, and clusters are provided. The mechanisms can be implemented during reset or while a system is operating. Links can be dynamically enabled or disabled.

An apparatus and method for expediting the processing of requests in a multiprocessor shared memory system. In a multiprocessor shared memory system, requests can be processed in any order provided two rules are followed. First, no request that grants access rights to a processor can be processed before an older request that revokes access rights from the processor. Second, all requests that reference the same cache line are processed in the order in which they arrive. In this manner, requests can be processed out-of-order to allow cache-to-cache transfers to be accelerated. In particular, foreign requests that require a processor to provide data can be processed by that processor before older local requests that are awaiting data. In addition, newer local requests can be processed before older local requests. As a result, the apparatus and method described herein may advantageously increase performance in multiprocessor shared memory systems by reducing latencies associated with a cache consistency protocol.

A distributed shared memory system includes a plurality of nodes. Each of the nodes includes a plurality of shared multiprocessors. Each of the shared multiprocessors includes a processor, a shared cache, and a memory. Each of the nodes includes a coherence maintaining unit that maintains cache coherence based on a plurality of directories each of which corresponding to each of the shared caches included in the distributed shared memory system.

A system, apparatus and method of reducing cache thrashing in a multi-processor with a shared cache executing a disruptive process (i.e., a thread that has a poor cache affinity or a large cache footprint) are provided. When a thread is dispatched for execution, a table is consulted to determine whether the dispatched thread is a disruptive thread. If so, a system idle process is dispatched to the processor sharing a cache with the processor executing the disruptive thread. Since the system idle process may not use data intensively, cache thrashing may be avoided.

Disclosed is a method and system for automatically forming a group to share a media file or adding the media file to an existing group. The method and system includes receiving, by a processor, a media file comprising an image, identifying, by the processor, the face of a first person in the image and the face of a second person in the image, identifying, by the processor, a first profile of the first person from the face of the first person and a second profile of the second person from the face of the second person, automatically forming, by the processor, a group of recipients in a messaging application, the forming of the group of recipients based on the first profile and the second profile, the group of recipients comprising the first person and the second person; and sharing, by the processor, the media file with the group.

Cooperatively scheduling hardware resources by providing information on shared resources within processor packages to the operating system. Logical processors may be included in packages in which some or all processor execution resources are shared among logical processors. In order to better schedule thread execution, information regarding which logical processors are sharing processor execution resources and information regarding which system resources are shared among processor packages is provided to the operating system. Extensions to the SRAT (static resource affinity table) can be used to provide this information.

The multiprocessing apparatus of the present invention is a multiprocessing apparatus including a plurality of processors, a shared bus, and a shared bus controller, wherein each of the processors includes a central processing unit (CPU) and a local cache, each of the local caches includes a cache memory, and a cache control unit that controls the cache memory, each of the cache control units includes a data coherence management unit that manages data coherence between the local caches by controlling data transfer carried out, via the shared bus, between the local caches, wherein at least one of the cache control units (a) monitors a local cache access signal, outputted from another one of the processors, for notifying an occurrence of a cache miss, and (b) notifies pseudo information to the another one of the processors via the shared bus controller, the pseudo information indicating that data corresponding to the local cache access signal is stored in the cache memory of the local cache that includes the at least one of the cache control units, even in the case where the data corresponding to the local cache access signal is not actually stored.

A multiprocessor system may have a plurality of processors and a memory unit. Each of the processors may include at least one cache memory. The memory unit may be shared by two of the processors. The multiprocessor system may further include a control unit. If the multiprocessor system receives an access request for a data block of the memory unit from one processor, the control unit may forward an interrupt signal to another processor that shares the requested data block. The directory memory may store information indicating the processors that share data blocks of the memory unit. A memory controller unit may include the memory unit, the directory memory, and a control unit connected to memory unit and the directory memory. Each of the processors may include a processor core including a write buffer and a cache memory. The processors may also include a processing unit. When the processor shares a data block, the processing unit may invalidate the shared data block in the cache memory, write the shared data block from the write buffer to a memory unit, and forward an interrupt completion response to a control unit. When the processor attempts to obtain data, the processing unit may forward an access request for a data block of a memory unit, receive a retry request signal from a control unit, and insert the data block into the cache memory of the processor upon receiving an authorization signal from the control unit.

The invention provides a method and a device for sending/receiving data on the basis of processor shared memory, wherein the data-sending method based on processor shared memory comprises the following steps of writing data into at least one memory block in a shared memory pool of a processor, generating a memory block pointer according to the address information of the memory block and sending the memory block pointer to a receiver. The invention also provides a data-sending device based on processor shared memory, as well as a method and a device for receiving data on the basis of processor shared memory. As the invention adopts a technical means of transmitting the memory block pointer instead of message data, the invention has the advantages of solving the problem that the message data is repeatedly copied during message transmission and achieving the technical effect of reducing overhead for both memory and time.

The invention discloses an interrupt controller and a method for processing interrupt of a multi-core processor shared device. The interrupt controller monitors interrupt load on each core of a multi-core processor through a cycle timer, the routing policy of the interrupt controller is timely adjusted dynamically, the balance of the interrupt load among a plurality of cores is guaranteed, and the potential of a multi-core structure is fully exerted. The method comprises the following steps that: a, a threshold value of an interrupt load statistic is preset; b, the interrupt controller receives a request from a shared interrupt source and adjusts a routing mode of the interrupt controller according to the current interrupt load statistic; c, the interrupt controller routes the interrupt request to the core according to the routing mode; and d, the core is subjected to an interrupt processing routine.

In a particular embodiment, a method of monitoring interrupts during a power down event at a processor includes activating an interrupt monitor to detect interrupts. The method also includes isolating an interrupt controller of the processor from the interrupt monitor, where the interrupt controller shares a power domain with the processor. The method also includes detecting interrupts at the interrupt monitor during a power down time period associated with the power down event.

Provided are a method and apparatus for checking the integrity of firmware. The method includes storing a first hash function value of unhacked firmware for determining whether actual firmware of an external processor has been hacked; reading the actual firmware via a bus; calculating a second hash function value of the actual firmware; comparing the first hash function value with the second hash function value; and sharing a bus key with the external processor, based on the comparison result.

To be achieved in the present invention is a cache coherency control, wherein scalability of a shared-memory type multiprocessor system is improved, and cost-performance is improved by restraining the cost of hardware and software. In a system for controlling cache coherency of a multi-processor system wherein a plurality of processors comprising caches and TLBs share system memory, each of the processors comprises a TLB control unit further comprising: a TLB searching unit for executing TLB searching; and a coherency handler for executing registration information processing of the TLB, when no hit is obtained in the TLB searching and a TLB interruption is generated. The coherency handler comprises: a TLB replacement handler for executing a search of a page table of the system memory, and registration information replacement of the TLB; a TLB-mistake exception handling unit for handling a TLB-mistake interruption, which occurs when the TLB interruption is not caused by a page fault, but registration information that matches the address does not exist in the TLB; and a storage exception handling unit for handling a storage interruption, which occurs when registration information that matches the address exists in the TLB, but accessing authority is infringed.

The invention embodiment discloses a method of polycaryon processor sharing code segment mend, which is more particularly that: the visiting right for the prearranged code mend area and the sharing code segment is opened and mend synchronization information is sent to the operation vCPU; whether all the operation vCPU finishes synchronization is checked, and mend operation is conducted if all synchronizations are finished. The invention also discloses a polycaryon processor sharing code segment mend device, which comprise a right control unit, a transmission unit and a control unit. Owning to the method of synchronization multi business vCPU, the invention resolves the reliability of polycaryon CPU mend operation and realizes the mend technology under the condition of polycaryon processor sharing code segment.

A system and method for using a handler to detect asynchronous lock line reservation lost events, and switching tasks based upon whether a condition is true or a mutex lock is acquired is presented. A synergistic processing unit (SPU) invokes a first thread and, during execution, the first thread requests external data that is shared with other threads or processors in the system. This shared data may be protected with a mutex lock or other shared memory synchronization constructs. When requested data is not available, the SPU switches to a second thread and monitors lock line reservation lost events in order to check when the data is available. When the data is available, the SPU switches back to the first thread and processes the first thread's request.