12 results about "Processor sharing" patented technology

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to read utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the utilization-related information for the resource. Other embodiments are disclosed and claimed.

Various example embodiments of a capability for supporting fast warmup of a processor cache are presented. The processor cache may be a processor-side cache that is disposed within a processing unit (e.g., a cache within a processor of the processing unit, a cache within the processing unit where the cache is shared by multiple processors of the processing unit, or the like). The fast warmup of the processor cache may be supported based on a persistent memory. The fast warmup of the processor cache may be supported based on a persistent memory by storing the contents of the processor cache from the processor cache into the persistent memory based on a reset of the processing unit and storing the contents of the processor cache from the persistent memory into the processor cache based on a restart of the processing unit.

According to certain implementations, a motherboard is provided that enables operation as either multiple independent single-processor systems or a single multiple-processor system. In response to a request to configure the motherboard as multiple independent single-processor systems, a control block is implemented for each processor attached to the motherboard, where the control blocks configure the processors to boot and operate independently of each other, and the processors utilize separate motherboard resources. In response to a request to configure the motherboard as multiple independent single-processor systems, a single control block is implemented all processors attached to the motherboard, where the single control block configures all processors to boot and operate in a connected state, and the processors share all motherboard resources.

In a processing system with multiple processors, a shared cache memory is allocated. [Solution] The processing systems 100 and 100a that process tasks include a plurality of processors 10 and 20, a shared cache memory 30 shared by the plurality of processors, a resource manager 50 that allocates, for each task to be executed, an execution processor from among the plurality of processors to execute the task, and a memory area to be used in the shared cache memory, and a first profile storage unit 60 that stores a cache partitioning profile 61 in which area-related information, which is information about the memory area to be used, is set for each type of task. The resource manager uses the area-related information according to the type of task to be executed in the cache partitioning profile to perform the allocation.

The invention provides an engineering control device, system and method. The engineering control device comprises a first processor and a second processor, and the first processor is in communication connection with an upper computer; the second processor is in communication connection with the first processor and shares a memory with the first processor, the first processor is at least used for acquiring a configuration parameter file in an upper computer, and the configuration parameter file is used by the first processor and the second processor; the second processor is used for receiving the configuration parameter file obtained by the first processor from the memory; wherein the first processor is further used for responding to failure of sending the configuration parameter file to the second processor, sending a detection signal to the second processor and determining whether the second processor works normally or not based on whether a feedback signal is received or not, and the feedback signal should be generated and sent by the second processor in response to the detection signal. According to the scheme, the safety of the engineering control device can be improved.

A multi-processor device comprises more than two processors. The multi-processor device can make the two processors running different operating systems (for example, Linux, real-time operating system (RT OS) or non-operating system (non-OS)) share one peripheral controller by allocating transmit descriptions, receive descriptions, transmit buffers corresponding to the transmit descriptions and receive buffers corresponding to the receive descriptions of the two processors in a shared memory. The peripheral device can process the data associated with the two processors. In one embodiment, the peripheral controller can be an Ethernet controller, and the peripheral device is an Ethernet network card.

Systems, devices, methods, and machine-readable media for attestation verifiers are described. For example, one embodiment of a device includes a first instance of a verifier associated with a first application, the first instance allowing a user of the first application to attest to a first relying party, a secure key store accessible by the first instance of the verifier, the secure key store securely storing attestation data related to the first application, and a synchronization processor sharing at least a portion of the attestation data with a second instance of the verifier associated with a second application to be executed on the device.

This invention relates to a method for allocating and releasing shared register files in a unified coloring graphics processor. The method includes the following steps: 1) dividing the physical memory unit into 8 banks and 128 blocks; 2) establishing a block allocation and release table; 3) integrating the physical memory unit division and the block allocation and release table to achieve the conversion from logical addresses to physical register addresses; 4) allocating and releasing data based on the physical register addresses, using one or more blocks as the scheduling unit. This invention solves the problem of limited coloring kernel size caused by the exclusive use of register files by the coloring kernel, and has the advantage of improving the utilization rate of the unified coloring array registers.

This invention relates to a conflict detection and queuing method for shared register file grouping mapping in a unified coloring graphics processor. The method includes the following steps: 1) Physical storage units are divided into 8 banks. Each warp is allocated 16 read operand addresses and 8 write operand addresses for operand collection. These 16 read operand addresses and 8 write operand addresses are decoded and mapped to the 8 banks; 2) A hierarchical grouping address mapping method with pipelined architecture is used. This is achieved by grouping the 16 read operand addresses and 8 write operand addresses of each bank and establishing a pipeline for mapping. This invention primarily addresses the access process of register files, providing a conflict detection and queuing mechanism to resolve bank conflicts that may occur during actual transmission.

This invention discloses a main control chip, a solid-state drive (SSD), a key management method thereof, and a computer storage medium, relating to the field of memory technology. The main control chip includes: a business subsystem, comprising a business core processor, shared memory, and key volatile memory, used for using keys; a security subsystem, communicatively connected to the business subsystem, comprising a security core processor, a true random number generator, a low-speed encryption / decryption engine, and a one-time programmable memory, used for key management; a configuration register, communicatively connected to the business subsystem; and a high-speed encryption / decryption engine, communicatively connected to both the business subsystem and the configuration register. This invention adds a security subsystem to the main control chip, thereby separating key management permissions and reducing the possibility of key leakage.

The invention relates to a data processing method and device, electronic equipment and a storage medium. The data processing method comprises the following steps: if a target thread is an important thread, taking a first cache region as a target storage region; if the target thread is a non-important thread, taking the second cache region as a target storage region; the cache data of the target thread is stored in a target storage area, the first cache area and the second cache area are partial storage areas in the processor shared cache, and the first cache area is larger than the second cache area; or, the first cache region is the whole storage region in the processor shared cache, and the second cache region is the storage region in the memory. According to the method, the threads are classified according to the importance degree, cache data storage areas between different thread types are isolated, cache resources are inclined, the performance and response speed of the important threads can be improved, it is ensured that an application program runs smoothly and stably, and the use experience of a user is improved.

A computing system (20) comprising a memory A (30), a memory access control module (50), and a parallel processing processor (40) comprising a plurality of computing units (41) each comprising a memory B shared by one or more elementary processors (43). The computing units are arranged in a column. A partition (31) of the memory A is associated with each column. Connection modules (60) are connected respectively to the partitions of the memory A and to the memories B of the computing units (41). Within a column, the neighboring connection modules are connected to each other by a dedicated interface link (61). The memory access control module (50) is adapted to configure the connection modules (60) to execute data transfers in parallel in several columns, each transfer allowing an exchange of data within a column between a partition of the memory A and a memory B of at least one computing unit.Figure for abstract: Fig. 2.