Method and device for accessing memory

Abstract

The invention discloses a method and equipment for accessing a memory, relates to the technical field of terminals, and can solve the problem that a terminal device with a multiprocessor architecture cannot realize scientific and ordered memory access. In the application, the plurality of processors of the terminal equipment share the same memory, so that any processor can be ensured to normally store data, modify or read stored data and the like in any use scene. Moreover, any one of the plurality of processors can realize mutual exclusion access of the plurality of processors to the memory based on the acquired condition that whether other processors are accessing the memory or not, so that more scientific and ordered memory sharing is realized. According to the scheme that the processors of the terminal equipment share the same memory, the production cost of the terminal equipment can be reduced, and support is provided for miniaturization of the terminal equipment.

Description

Technical Field

[0001] This application relates to the technical field of terminals, and in particular, to a method and device for accessing a memory. Background Art

[0002] Currently, due to considerations such as business functions and battery life, some terminal devices adopt a multi-processor architecture. For example, some terminal devices include dual processors, such as a main processor and a coprocessor. For a terminal device with a multi-processor architecture, how to perform access to the memory by multiple processors is a problem to be solved. Summary of the Invention

[0003] This application provides a method and device for accessing a memory, which can solve the problem that a terminal device with a multi-processor architecture cannot achieve scientific and orderly memory access.

[0004] To achieve the above object, this application adopts the following technical solutions:

[0005] In a first aspect, a method for accessing a memory is provided. The method is applied to a first processor in a terminal device. The terminal device further includes a second processor and a memory in addition to the first processor. The first processor and the second processor share the memory. The method includes: the first processor receives a service request for requesting access to the memory from an application; the first processor obtains first information from the second processor for characterizing whether the second processor is accessing the memory; when the first information characterizes that the second processor is not accessing the memory, the first processor accesses the memory in response to the service request.

[0006] For the solution provided in the above first aspect, multiple processors (such as the first processor and the second processor) of the terminal device can ensure that any processor can normally perform data storage, modification, or reading of stored data, etc. in any usage scenario by sharing the same memory. Moreover, any one of the multiple processors (such as the first processor) can implement mutually exclusive access to the memory by multiple processors based on the access situation of other processors (such as the second processor) to the memory, such as whether other processors are accessing the memory, so as to achieve more scientific and orderly sharing of the memory. In addition, the solution of sharing the same memory by multiple processors (such as the first processor and the second processor) of the terminal device can also reduce the production cost of the terminal device and support the miniaturization of the terminal device.

[0007] As an example, the first information may characterize whether the second processor is accessing the memory in a plaintext form, such as a direct indication or other plaintext forms; or the first information may characterize whether the second processor is accessing the memory in an implied form, such as a parameter representation, a preset action (such as not replying) representation, etc. This application does not make a limitation.

[0008] As an example, the first processor can directly obtain information from the second processor for characterizing whether the second processor is accessing the memory. However, this application does not limit the specific manner and process of the first processor and obtaining the information for characterizing whether the second processor is accessing the memory. For example, in some examples, the first processor can also obtain the information for characterizing whether the second processor is accessing the memory from a third party, such as a status storage unit.

[0009] As an example, the first processor is an application processor (AP), and the second processor is a microprogrammed control unit (MCU); alternatively, the first processor is an MCU, and the second processor is an AP; the memory is an embedded multi media card (eMMC). Of course, the first processor or the second processor may also be other devices, modules or chips with other structures or functions, which are not limited in this application.

[0010] As a possible implementation, the first processor includes a first pin, the second processor includes a second pin, and the first pin is connected to the second pin. The first processor obtaining the first information from the second processor includes: the first processor obtaining the status of the first pin, and the status of the first pin is used for characterizing whether the second processor is accessing the memory. It can be understood that since the first pin of the first processor is connected to the second pin of the second processor, the first pin can sense the status of the second pin. Based on this, the first pin can identify whether the second processor is accessing the memory through the sensed status of the second pin. This solution provides a more convenient, low-cost, low-power and accurate implementation for obtaining the situation of other processors accessing the memory.

[0011] As a possible implementation, the status of the first pin includes a first level and a second level. The method further includes: if the status of the first pin is the first level, it is determined that the second processor is accessing the memory; if the status of the first pin is the second level, it is determined that the second processor is not accessing the memory. Based on this, a more convenient, low-cost, low-power and accurate implementation for obtaining the situation of other processors accessing the memory can be provided.

[0012] As an example, the first level is a high level, and the second level is a low level; alternatively, the first level is a low level, and the second level is a high level, which is not specifically limited in this application.

[0013] As a possible implementation, when the state of the second pin is at the third level, the state of the first pin is at the first level; when the state of the second pin is at the fourth level, the state of the first pin is at the second level. Based on this, it is possible to support the first processor to sense the state of the second pin according to the state of the first pin, and then accurately determine whether the second processor is accessing the memory, so as to obtain the situation of the second processor accessing the memory conveniently and accurately.

[0014] As an example, the third level is, for example, a high level, and the fourth level is, for example, a low level; or, the third level is, for example, a low level, and the fourth level is, for example, a high level. The present application does not make specific limitations.

[0015] As a possible implementation, the first processor further includes a third pin, and the state of the third pin represents whether the first processor is accessing the memory. Based on this, it is convenient for other processors to know whether the first processor is accessing the memory, so as to prevent conflicts caused by multiple processors accessing the memory simultaneously, and achieve a more scientific and orderly sharing of the memory.

[0016] As a possible implementation, when the first processor accesses the memory, the state of the third pin is at the fifth level; when the first processor does not access the memory, the state of the third pin is at the sixth level. Based on this, it is possible to conveniently and accurately notify other processors whether the first processor is accessing the memory.

[0017] As an example, the fifth level is, for example, a high level, and the sixth level is, for example, a low level; or, the fifth level is, for example, a low level, and the sixth level is, for example, a high level. The present application does not make specific limitations.

[0018] As a possible implementation, the above method further includes: before the first processor accesses the memory, adjusting the state of the third pin from the sixth level to the fifth level. Based on this, it is convenient for other processors to know whether the first processor is accessing the memory, so as to prevent conflicts caused by multiple processors accessing the memory simultaneously, and achieve a more scientific and orderly sharing of the memory.

[0019] As a possible implementation, the above-mentioned first processor adjusts the state of the third pin from the sixth level to the fifth level, including: after receiving a service request, the first processor obtains second information from the second processor for characterizing whether the second processor accesses the memory; when the second information indicates that the second processor does not access the memory, the first processor adjusts the state of the third pin from the sixth level to the fifth level. Based on this, the first processor adjusts the state of the third pin when about to start accessing the memory to timely notify other processors whether the first processor is accessing the memory. In addition, to avoid a conflict caused by the second processor starting to access the memory after the first processor determines that the state of the first pin is the second level based on the second information and then determines that the second processor does not access the memory, resulting in the first processor and the second processor accessing the memory simultaneously, the first processor can again determine whether the second processor accesses the memory by obtaining the first information to ensure that the first processor does not access the memory simultaneously with the second processor.

[0020] As a possible implementation, the above-mentioned first processor obtains first information from the second processor, including: when the second information indicates that the second processor is accessing the memory, waiting for a preset duration and then obtaining the first information from the second processor. Based on this, it is possible to avoid waste of power consumption, processing resources, etc. of the terminal device caused by the first processor continuously obtaining first information from the second processor.

[0021] As a possible implementation, the above-mentioned memory includes: a partition corresponding to the first processor and not corresponding to the second processor, and a partition corresponding to both the first processor and the second processor. The above-mentioned service request is used to request access to one or more of the following partitions in the memory: the partition corresponding to the first processor and not corresponding to the second processor, and the partition corresponding to both the first processor and the second processor. Based on this, regardless of which partition of the memory the first processor accesses, data storage, modification, or reading of stored data can be performed normally, and more scientific and orderly sharing of the memory by multiple processors can be achieved.

[0022] As an example, the above-mentioned memory further includes a partition corresponding to the second processor and not corresponding to the first processor. Of course, the present application does not limit the specific partitions of the memory. For example, the memory may not include exclusive partitions corresponding to the first processor or the second processor.

[0023] As a possible implementation, the above-mentioned first processor accesses the memory to perform one or more of the following: reading data in the memory, writing data to the memory, and modifying data in the memory. Based on this, regardless of the purpose of the first processor accessing the memory, data access can be performed normally, and more scientific and orderly sharing of the memory by multiple processors can be achieved.

[0024] In a second aspect, a chip is provided, which includes a processing module and one or more pins. The processing module and the one or more pins are used to enable the chip to implement the method in any possible implementation manner of the first aspect.

[0025] As an example, the chip is such as an AP or an MCU, etc.

[0026] In a third aspect, a terminal device is provided, which includes: a first processor, a second processor, and a memory. The first processor and the second processor share the memory, and the first processor or the second processor is used to implement the method in any possible implementation manner of the first aspect.

[0027] In a fourth aspect, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the method in any possible implementation manner of the first aspect is implemented.

[0028] In a fifth aspect, a computer program product containing instructions is provided. When the computer program product runs on a computer, the computer is enabled to implement the method in any possible implementation manner of the first aspect.

[0029] In a sixth aspect, a chip system is provided, which includes a processing circuit and a storage medium. Computer program instructions are stored in the storage medium; when the computer program instructions are executed by the processor, the method in any possible implementation manner of the first aspect is implemented. The chip system may be composed of chips, or may include chips and other discrete devices. Description of the Drawings

[0030] Figure 1 It is a schematic structural diagram of a terminal device including a dual-processor and dual-memory architecture;

[0031] Figure 2 It is a schematic hardware structure diagram of a terminal device provided in an embodiment of the present application;

[0032] Figure 3 It is a schematic structural diagram of a terminal device provided in an embodiment of the present application, in which a main processor and a coprocessor share the same memory;

[0033] Figure 4 It is a schematic diagram of a storage area partitioning method of a memory provided in an embodiment of the present application;

[0034] Figure 5 It is a schematic software structure diagram of a terminal device provided in an embodiment of the present application;

[0035] Figure 6An architecture diagram of a memory access process provided by an embodiment of the present application;

[0036] Figure 7 Another architecture diagram of a memory access process provided by an embodiment of the present application;

[0037] Figure 8 An architecture diagram of an interaction process when accessing a memory provided by an embodiment of the present application;

[0038] Figure 9 A flowchart of a method for accessing a memory provided by an embodiment of the present application;

[0039] Figure 10 Another flowchart of a method for accessing a memory provided by an embodiment of the present application;

[0040] Figure 11 A flowchart of a process for accessing a memory provided by an embodiment of the present application. Detailed implementation manners

[0041] Next, the technical solutions in the embodiments of the present application will be described in conjunction with the accompanying drawings in the embodiments of the present application. Among them, in the description of the embodiments of the present application, unless otherwise specified, " / " means "or". For example, A / B may mean A or B; herein, "and / or" is only an association relationship describing associated objects, indicating that three relationships may exist. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality of" means two or more than two.

[0042] Hereinafter, terms such as "first", "second", etc. are only used to distinguish different described objects, and do not limit the position, order, priority, quantity, content, etc. of the described objects. For example, if the described object is "field", the ordinal numbers before "field" in "first field" and "second field" do not limit the position or order between the "fields", and "first" and "second" do not limit whether the "fields" they modify are in the same message, nor do they limit the order of "first field" and "second field". For another example, if the described object is "level", the ordinal numbers before "level" in "first level" and "second level" do not limit the priority between the "levels". For another example, the quantity of the described object is not limited by the ordinal number and can be one or more. Taking "first device" as an example, the quantity of "device" therein can be one or more. In addition, the objects modified by different prefix words can be the same or different. For example, if the described object is "device", "first device" and "second device" can be devices of the same type or different types. For another example, if the described object is "level", "first level" and "second level" can be the same level or different levels. In short, in the embodiments of the present application, the use of ordinal numbers and other prefix words for distinguishing described objects does not constitute a limitation on the described objects. For the statement of the described objects, refer to the description in the claims or the context of the embodiments, and no redundant limitation should be formed due to the use of such prefix words.

[0043] In addition, in the embodiments of the present application, "connection" can be a direct connection or an indirect connection; in addition, it can refer to an electrical connection or a communication connection; for example, when two electrical components A and B are connected, it can mean that A is directly connected to B, or it can mean that A and B are indirectly connected through other electrical components or connection media, or it can mean that A and B are indirectly connected through other communication devices or communication media, as long as communication can be carried out between A and B.

[0044] As described in the background art, for reasons such as business functions and battery life, some terminal devices adopt a multi-processor architecture such as a dual-processor architecture. For example, a dual-processor architecture of a main processor and a coprocessor is adopted. As an example, a terminal device may include an application processor (AP) and a microprogrammed control unit (MCU). Among them, the AP is mainly responsible for running the operating system and multimedia applications, and the AP is such as a system on chip (SOC), etc.; the MCU is sometimes also called a single-chip microcomputer and is mainly used for signal control. Due to the characteristics of low cost and low power consumption of the MCU, it can also be used for some simple operations.

[0045] As a possible structure, the terminal device further includes a memory that provides data storage services for the AP, such as an embedded multi media card (eMMC). Based on this, the MCU can interact with the AP to achieve the purpose of storing MCU-related data by means of the memory configured for the AP.

[0046] With the diversified development of terminal devices and the need for low power consumption of terminal devices, more and more terminal devices support low power consumption modes (such as super power saving mode, without limiting the specific mode name). In the low power consumption mode, some idle hardware modules can be powered down to save the power consumption of the terminal device. For example, in the low power consumption mode, the AP of the terminal device and the memory configured for it (such as eMMC) may be powered down, while the MCU works normally. In this case, since the power down of the AP and the memory will cause the MCU to be unable to perform normal data storage and normal reading, modification, deletion, etc. of the data stored in the memory.

[0047] To solve the above problems existing in the terminal device in the low power consumption mode, as a possible structure, the terminal device may include multiple memories respectively configured for multiple processors. For example, the terminal device may adopt an architecture of dual processors and dual memories. As Figure 1 shown, the terminal device may include eMMC1 and eMMC2 respectively configured for the AP and the MCU. Among them, the AP and the MCU can be respectively connected to eMMC1 and eMMC2 through a secure digital input and output (SDIO) interface (such as Figure 1 the SDIO1 and SDIO2 shown), and the AP and the MCU can be connected through Figure 1 the serial peripheral interface (SPI) described above to perform relevant interactions. Based on this, whether in the normal mode or the low power consumption mode, the MCU can normally perform data storage and normal reading, modification, deletion, etc. of the stored data.

[0048] However, Figure 1 the architecture of dual processors and dual memories causes the fragmentation of the storage spaces corresponding to the AP and the MCU, which will lead to the data of some applications related to both the AP and the MCU (such as music, etc.) being written into both memories of eMMC1 and eMMC2 at the same time. In addition, the cost of the dual memories is relatively high, and it will affect the layout of the hardware in the terminal device. Especially in the current diversified development of terminal devices, the challenges in cost and layout may pose a greater obstacle to the requirements of the device for lower cost and smaller size.

[0049] To solve the above problems existing in the terminal device with a dual-processor and dual-memory architecture, and to solve the problems that in a terminal device with a dual-processor and single-memory structure, the MCU cannot perform normal data storage and the normal reading, modification, and deletion of the data stored in the memory in the low-power mode, the embodiments of the present application provide a solution in which multiple processors share the same memory. In this solution, the terminal device includes multiple processors, such as a main processor and a coprocessor, and the multiple processors share the same memory. Based on this, compared with the architecture in which the MCU stores MCU-related data by means of the memory configured for the AP, even when the AP and the memory configured for the AP are powered off in the low-power mode, the storage of MCU-related data and the normal reading, modification, deletion, etc. of the stored data can still be carried out normally.

[0050] Moreover, compared with Figure 1 the dual-processor and dual-memory architecture shown, the solution provided by the embodiments of the present application can avoid the problem that data of some applications related to both the AP and the MCU is written repeatedly, can also reduce the production cost of the terminal device, and provides support for the miniaturization of the terminal device.

[0051] In addition, in the solution provided by the embodiments of the present application, multiple processors of the terminal device can share the same memory, and any one of the multiple processors can realize the mutually exclusive access of the multiple processors to the memory based on the situation of other processors accessing the memory, such as the information on whether other processors are accessing the memory, so as to realize a more scientific and orderly sharing of the memory.

[0052] Among them, the terminal device described in the embodiments of the present application may include but is not limited to smartphones, netbooks, tablet computers, smart drawing boards, writing tablets, smart watches, smart bracelets, phone watches, smart glasses, smart cameras, palm computers, in-vehicle computers, personal computers (PCs), personal digital assistants (PDAs), portable multimedia players (PMPs), augmented reality (AR) / virtual reality (VR) devices, smart TVs, projection devices, or somatosensory game consoles in a human-computer interaction scenario, etc. Alternatively, the terminal device may also be other types or structures of terminal devices, which are not limited in the present application.

[0053] As an example, please refer to Figure 2 , Figure 2 Taking a terminal device including a main processor and a coprocessor, where the main processor and the coprocessor share the same memory as an example, a schematic diagram of the hardware structure of a terminal device provided by the embodiments of the present application is shown.

[0054] As Figure 2 shown, the terminal device may include a main processor, a coprocessor, a memory, an audio module, a speaker, a microphone, a display screen, a camera, and a sensor module, etc. Among them, the sensor module may include, as Figure 2 shown, an acceleration sensor, a gyroscope sensor, a magnetic sensor, a gravity sensor, a bone conduction sensor, etc. In some possible structures, the sensor module may further include other types of sensors such as a touch sensor, a pressure sensor, a barometric pressure sensor, a distance sensor, a proximity light sensor, a fingerprint sensor, an ambient light sensor, etc., which are not specifically limited in the embodiments of the present application.

[0055] The main processor is mainly responsible for running the operating system and multimedia applications, such as being responsible for the management and maintenance of application information and application-related user information, and being responsible for the implementation of system functions (such as music playback function, dial function), etc. The main processor may include, but is not limited to, an AP, etc. The coprocessor is mainly used for signal control and some simple operations, such as performing music player-related control, performing dial-related control, performing measurement control of the sensor module, performing relevant calculations on the data collected by the sensors, etc. The coprocessor may include, but is not limited to, a low-power processor such as an MCU.

[0056] The terminal device can implement audio functions through the audio module, the speaker, the microphone, and the AP, etc. For example, music playback, recording, etc.

[0057] The audio module is used to convert digital audio information into an analog audio signal for output, and is also used to convert analog audio input into digital audio signals. The audio module can also be used for encoding and decoding audio signals. In some embodiments, the audio module may be disposed in the main processor, or some functional modules of the audio module may be disposed in the main processor.

[0058] The speaker, also known as the "loudspeaker", is used to convert an audio electrical signal into a sound signal. The terminal device can listen to music or listen to a hands-free call through the speaker.

[0059] The microphone, also known as the "microphone", "transmitter", is used to convert a sound signal into an electrical signal. When making a call or sending a voice message, the user can speak close to the microphone with their mouth to input the sound signal into the microphone. The terminal device may be provided with at least one microphone C. In some other embodiments, the terminal device may be provided with two microphones, which can not only collect sound signals but also implement a noise reduction function. In some other embodiments, the terminal device may also be provided with three, four or more microphones to implement sound signal collection, noise reduction, and can also identify the sound source to implement a directional recording function, etc.

[0060] An acceleration sensor (or accelerometer) can detect the magnitude of acceleration of a terminal device in various directions (generally three axes). When the terminal device is stationary, it can detect the magnitude and direction of gravity, and can also be used to identify the posture of the terminal device, etc., and is applied to applications such as pedometers. In some embodiments, the terminal device can obtain the user's movement direction, movement speed, etc. based on the data detected by the acceleration sensor.

[0061] A gyroscope sensor can be used to determine the movement posture of a terminal device during movement. In some embodiments, the rotation direction and rotation angular velocity of the terminal device around three axes (i.e., the x, y, and z axes) can be determined by the gyroscope sensor.

[0062] A magnetic sensor such as a Hall sensor is a device that converts changes in the magnetic properties of a sensitive element caused by external factors such as magnetic fields, currents, stress and strain, temperature, and light into electrical signals, and detects the corresponding physical quantities in this way. In some embodiments, the angles between the terminal device and the four directions of east, south, west, and north can be measured by the magnetic sensor.

[0063] A gravity sensor can be used to detect the magnitude and direction of the gravity received by a terminal device. In some embodiments, the terminal device can obtain information such as the user's location and height based on the data detected by the gravity sensor.

[0064] A bone conduction sensor can acquire vibration signals. In some embodiments, the bone conduction sensor can acquire the vibration signals of the vibrating bone mass of the human vocal part. The bone conduction sensor can also contact the human pulse and receive blood pressure pulsation signals. In some embodiments, the heart rate information can be analyzed based on the blood pressure pulsation signals acquired by the bone conduction sensor to realize functions such as heart rate detection and sleep detection.

[0065] The display screen is used to display images, videos, etc. The display screen includes a display panel. The display panel can adopt a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active matrix organic light-emitting diode or an active matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a Miniled, a MicroLed, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc.

[0066] The memory can be used to store computer-executable program code. Exemplarily, the computer program can include an operating system program and application programs. Among them, the executable program code includes instructions. The main processor or coprocessor executes various functional applications and data processing of the terminal device by running the instructions stored in the memory.

[0067] Taking the main processor as the AP and the coprocessor as the MCU as an example, the memory can be used to store AP-related data and MCU-related data. AP-related data such as AP system data, AP application data for implementing different functions, etc. MCU-related data such as sensorhub system data, sensorhub application data, sensor module-related data (such as motion, health data, etc.). The embodiments of the present application do not make specific limitations.

[0068] As an example, the memory can be an eMMC, or the memory can include an eMMC.

[0069] In the embodiments of the present application, the memory can include a program storage area and a data storage area. Among them, the program storage area can store the operating system, application programs required for at least one function, etc. The data storage area can store the data created during the use of the terminal device. In addition, the memory can include high-speed random access memory, and can also include non-volatile memory, such as at least one disk storage device, flash memory device, universal flash storage (UFS), etc. The main processor or coprocessor executes various functional applications and data processing of the terminal device by running the instructions stored in the memory.

[0070] It can be understood that the Figure 2 schematic structure does not constitute a specific limitation on the terminal device. In other embodiments of the present application, the terminal device can include more or fewer components than shown in the figure. For example, the terminal device can also include other one or more processing units such as a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a flight controller, a video codec, a digital signal processor (DSP), a baseband processor, a neural-network processing unit (NPU), etc. Different processing units can be independent devices or integrated in one or more processors. Another example is that the terminal device can also include one or more devices such as a charging management module, a power management module, a battery, an antenna, a mobile communication module, a wireless communication module, a button, an indicator, etc.

[0071] Alternatively, the terminal device can also combine certain components, or split certain components, or arrange different components. Figure 2 The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0072] As an example, please refer to Figure 3 , Figure 3 Taking, as an example, including a main processor and a coprocessor, and the main processor and the coprocessor sharing the same memory, a schematic structural diagram of a terminal device provided by an embodiment of the present application is shown. Among them, Figure 3 the main processor shown is such as an AP, the coprocessor is such as an MCU, and the memory shared by the main processor and the coprocessor is such as an eMMC.

[0073] In some embodiments, the memory may include multiple partitions, and the multiple partitions may include partitions exclusively occupied by the main processor and the coprocessor respectively, such as Figure 3 the first partition (i.e., the partition exclusively occupied by the main processor) and the second partition (i.e., the partition exclusively occupied by the coprocessor) shown. Among them, in the embodiments of the present application, an exclusive partition refers to providing data access services for a certain specific processor, including providing data storage services, data reading services, etc., and not providing data access services for other processors. That is to say, Figure 3 the first partition of the memory shown is used to store data from the main processor and can support the main processor to read the data stored in the first partition, and the first partition cannot store data from the coprocessor and cannot support the coprocessor to read the data stored in the first partition; similarly, Figure 3 the second partition of the memory shown is used to store data from the coprocessor and can support the coprocessor to read the data stored in the second partition, and the second partition cannot store data from the main processor and cannot support the main processor to read the data stored in the second partition.

[0074] In some embodiments, in order to avoid the problem of duplicate writing of data related to applications related to both the AP and the MCU, as a possible structure, such as Figure 3 shown, in addition to including the first partition and the second partition exclusively occupied by the main processor and the coprocessor respectively, the memory can also include a third partition (i.e., a shared partition) that can be shared by the main processor and the coprocessor. Among them, Figure 3 the third partition shown can not only store data from the main processor and support the main processor to read the data stored in the third partition, but also store data from the coprocessor and support the coprocessor to read the data stored in the third partition.

[0075] In some embodiments, Figure 3 the first partition shown can be used to store relevant data related to functions or applications related to the main processor (such as an AP),Figure 3 The second partition shown can be used to store relevant data related to functions or applications associated with a coprocessor (such as an MCU). Figure 3 The third partition shown can be used to store relevant data related to functions or applications associated with both the main processor (such as an AP) and the coprocessor (such as an MCU).

[0076] As an example, please refer to Figure 4 , Figure 4 Taking the terminal device as a smart watch and the terminal device including an AP and an MCU as an example, a schematic diagram of the storage area division of a memory provided by an embodiment of the present application is shown. As Figure 4 shown, the memory, such as eMMC, may include a first partition exclusive to the AP, a second partition exclusive to the MCU, and a third partition shared by the AP and the MCU.

[0077] Among them, Figure 4 the first partition shown (such as the AP exclusive partition) can be used to store relevant data related to functions or applications associated with the AP, such as AP system data, application data of AP application programs corresponding to one or more functions provided by the AP (hereinafter referred to as "AP application data"). Exemplarily, the AP system data is instructions related to the AP system. The AP can execute various AP system functions of the terminal device by running the instructions related to the AP system stored in the first partition; and, the AP application data is instructions related to the AP application. The AP can execute the AP application functions of the terminal device and related data processing by running the instructions related to the AP application stored in the first partition.

[0078] As an example, as Figure 4 shown, the first partition may also include multiple sub - partitions, and different sub - partitions can be used to store different types of data, such as storing AP system data, AP application data, etc. respectively.

[0079] Figure 4The second partition shown (such as the MCU exclusive partition) can be used to store data related to functions or applications related to the MCU, such as sensor hub system data, application data, sensor module measurement data (such as motion, health data, etc.). Exemplarily, storing sensor hub system data such as instructions related to the sensor hub system, the MCU can execute various sensor hub system functions of the terminal device by running the instructions related to the sensor hub system stored in the second partition; sensor hub application data such as instructions related to the sensor hub application, the MCU can execute the MCU application functions of the terminal device and related data processing by running the instructions related to the sensor hub application stored in the second partition, and related data processing such as calculating and processing the sensor module measurement data to obtain the user's heart rate, sleep condition, step count, exercise and health condition, etc.; sensor module measurement data such as the user's heart rate data, sleep data, pedometer data, exercise and health data measured by the sensor module.

[0080] As an example, such as Figure 4 shown, the second partition may also include multiple sub - partitions, and different sub - partitions can be used to store different types of data, such as respectively used to store sensor hub system data and application data, sensor module measurement data, etc.

[0081] Figure 4 The third partition shown (such as the shared partition) can be used to store data related to functions or applications related to both the main processor (such as the AP) and the co - processor (such as the MCU), such as music, watch faces, etc.

[0082] As an example, please refer to Figure 5 , Figure 5 Taking the main processor as the AP and the co - processor as the MCU as an example, a schematic diagram of a software structure provided by an embodiment of the present application is shown. As Figure 5 shown, the terminal device may include an AP system, an MCU system, and a memory (such as eMMC). Among them, the AP system and the MCU system include an application layer, a framework layer (framework, FWK), and a kernel layer from top to bottom.

[0083] Among them, the application layer may include a series of applications. As Figure 5 shown, the application layer of the AP system may include applications such as music, watch faces, etc., and the application layer of the MCU system may include applications such as heart rate, pedometer, exercise and health, music, sleep, watch faces, etc.

[0084] The framework layer is used to provide application programming interfaces (application programming interface, API) and programming frameworks for the applications in the application layer. As Figure 5As shown, the framework layer of the AP system can provide a music framework, a dial framework, etc. for the upper-layer AP application, and the framework layer of the MCU system can provide a heart rate framework, a pedometer framework, a sports health framework, a music framework, a sleep framework, a dial framework, etc. for the upper-layer MCU application.

[0085] The kernel layer is the layer between hardware and software. The kernel layer can contain drivers corresponding to the hardware, such as Figure 5 The hardware is shown as a storage driver and one or more sensor drivers. Figure 5 The memory shown (such as eMMC) and one or more sensors, etc.

[0086] in, Figure 5 The memory shown (such as eMMC) can be used to store AP-related data and MCU-related data, AP-related data such as AP system data, AP application data for implementing different functions, etc., MCU-related data such as sensor hub system data, sensor hub application data, sensor module-related data (such as sports, health data, etc.), etc., which are not specifically limited in the embodiments of the present application. Figure 5 The sensors shown may include but are not limited to one or more of the following: speed sensors, gyroscope sensors, magnetic sensors and gravity sensors, bone conduction sensors, etc. The sensors can be used to measure one or more of the following data: heart rate data, sleep data, pedometer data, sports health data, etc.

[0087] Of course, the embodiments of the present application do not limit the specific hardware included in the terminal device. For example, the terminal device may also include one or more hardware such as a camera, a display screen (touch screen), a camera, a microphone, etc. Correspondingly, the kernel layer of the AP system and the MCU system of the terminal device may also include one or more drivers such as a camera driver, a display driver, and a microphone driver.

[0088] In some embodiments, Figure 5 As shown, the kernel layer may also include a file system related to file storage. The file system is mainly responsible for managing and storing file information, such as organizing and managing files stored on the memory. For example, the file system can be used to store metadata of one or more data in the memory, such as index node number, file size, access rights, creation time, modification time, location of data in the memory, etc.; for another example, the file system can be used to store directory entries of one or more data in the memory, such as the name of the data, index node pointer, and hierarchical association relationship with other directory entries.

[0089] In some embodiments, Figure 5As shown, the kernel layer may also include a virtual filesystem (VFS) that serves as an interface layer between the filesystem and the upper-layer service framework, abstracting the details of the filesystem so that different filesystems appear the same to the upper-layer system core and other processes running in the system. For example, the VFS may define a set of data structures and standard interfaces supported by all filesystems.

[0090] It should be noted that Figure 5 merely as an example of the software structure diagram of a terminal device, only the levels and software modules related to the solution of this application are simply listed. In practical applications, the software system of the terminal device, such as the AP system or the MCU system, may also include other levels and each level may also include other software modules for implementing one or more functions or services. In this regard, the embodiments of this application do not make specific limitations.

[0091] In some embodiments, when a certain processor has a need to access the memory, such as Figure 6 or Figure 7 when Application A in the first processor as shown has a need to access the memory, Application A may initiate a service request to access the memory to the filesystem 1 of the first processor. After receiving the service request from Application A, the filesystem 1 may call the storage driver 1 to obtain the specific situation of other processors (such as the second processor) accessing the memory, such as whether other processors (such as the second processor) are accessing the memory. If no processor is accessing the memory, the first processor responds to the service request of Application A and starts accessing the memory; if other processors (such as the second processor) are accessing the memory, the first processor temporarily does not respond to the service request of Application A and does not access the memory temporarily until no processor is accessing the memory.

[0092] Similarly, in Figure 6 or Figure 7 when Application B in the second processor as shown has a need to access the memory, Application B may initiate a service request to access the memory to the filesystem 2 of the second processor. After receiving the service request from Application B, the filesystem 2 may call the storage driver 2 to obtain the specific situation of other processors (such as the first processor) accessing the memory, such as whether other processors (such as the first processor) are accessing the memory. If no processor is accessing the memory, the second processor responds to the service request of Application B and starts accessing the memory; if other processors (such as the first processor) are accessing the memory, the second processor temporarily does not respond to the service request of Application B and does not access the memory temporarily until no processor is accessing the memory.

[0093] As a possible implementation, the storage driver of a processor can directly obtain from the storage driver of another processor whether the other processor is accessing the memory.

[0094] Exemplarily, as Figure 6 shown, the storage driver 1 of the first processor can directly obtain from the storage driver 2 of the second processor whether the second processor is accessing the memory. For example, pins are respectively arranged on the storage driver 1 of the first processor and the storage driver 2 of the second processor. For example, a first pin is arranged on the storage driver 1 of the first processor, and a second pin is arranged on the storage driver 2 of the second processor, and the first pin is connected to the second pin. Based on this, the first processor can obtain the state of the second pin by obtaining the state of the first pin, and further determine whether the second processor is accessing the memory. For example, assume that the second processor is accessing the memory. The state of the second pin is usually the third level. When the state of the second pin is the third level, the state of the first pin of the first processor connected to the second pin is the first level. Based on this, if the state of the first pin is the first level, the first processor can determine that the state of the second pin is the third level and further determine that the second processor is accessing the memory. Also, for example, assume that the second processor is not accessing the memory. The state of the second pin is usually the fourth level. When the state of the second pin is the fourth level, the state of the first pin of the first processor connected to the second pin is the second level. Based on this, if the state of the first pin is the second level, the first processor can determine that the state of the second pin is the fourth level and further determine that the second processor is not accessing the memory.

[0095] Similarly, as Figure 6As shown in the figure, the storage driver 2 of the second processor can directly obtain whether the first processor is accessing the memory from the storage driver 1 of the first processor. For example, a third pin is provided on the storage driver 1 of the first processor, and a fourth pin is provided on the storage driver 2 of the second processor, and the third pin is connected to the fourth pin. Based on this, the second processor can obtain the state of the third pin by obtaining the state of the fourth pin, and then determine whether the first processor is accessing the memory. For example, assume that the first processor is accessing the memory. The state of the third pin is usually the third level. When the state of the third pin is the third level, the state of the fourth pin of the second processor connected to the third pin is the first level. Based on this, if the state of the fourth pin is the first level, the second processor can determine that the state of the third pin is the third level and then determine that the first processor is accessing the memory. Another example, assume that the first processor is not accessing the memory. The state of the third pin is usually the fourth level. When the state of the third pin is the fourth level, the state of the fourth pin of the second processor connected to the third pin is the second level. Based on this, if the state of the fourth pin is the second level, the second processor can determine that the state of the third pin is the fourth level and then determine that the first processor is not accessing the memory.

[0096] As an example, the first level is, for example, a high level, and the second level is, for example, a low level; or, the first level is, for example, a low level, and the second level is, for example, a high level.

[0097] As an example, the third level is, for example, a high level, and the fourth level is, for example, a low level; or, the fourth level is, for example, a low level, and the third level is, for example, a high level.

[0098] As an example, the first pin, the second pin, the third pin, or the fourth pin is, for example, a general purpose input / output (GPIO) pin; of course, the first pin, the second pin, the third pin, and the fourth pin can also be other pins, and the embodiments of the present application do not make specific limitations.

[0099] As a possible implementation, as Figure 7 shown, a state storage unit may be included in the terminal device for storing state flag bits of each processor accessing the memory, such as state flag bits for identifying whether each processor is accessing the memory.

[0100] Exemplarily, in the process that the first processor writes data to or reads data from the memory through the storage driver 1 in response to a service request of Application A, a first tag may be stored in the status storage unit, and the first tag is used to identify that the first processor is accessing the memory. For example, the storage driver 1 of the first processor may write the first tag to the status storage unit when starting to access the memory and delete the first tag when ending the access to the memory. Based on this, during the process that the first processor accesses the memory, when Application B in the second processor has a need to access the memory, the second processor may determine that the first processor is accessing the memory according to the first tag obtained from the status storage unit.

[0101] Similarly, in the process that the second processor writes data to or reads data from the memory through the storage driver 2 in response to a service request of Application B, a second tag may be stored in the status storage unit, and the second tag is used to identify that the second processor is accessing the memory. For example, the storage driver 2 of the second processor may write the second tag to the status storage unit when starting to access the memory and delete the second tag when ending the access to the memory. Based on this, during the process that the second processor accesses the memory, when Application A in the first processor has a need to access the memory, the first processor may determine that the second processor is accessing the memory according to the second tag obtained from the status storage unit.

[0102] In the following embodiments, taking the way that the storage driver of the first processor directly obtains whether the second processor is accessing the memory from other processors, such as the storage driver of the second processor, as an example, the method for accessing the memory provided by the embodiments of the present application will be specifically introduced.

[0103] As an example, please refer to Figure 8 , Figure 8 Taking a terminal device including an AP and an MCU and an eMMC as the memory as an example, an interaction process architecture diagram when accessing the memory provided by the embodiments of the present application is shown. As Figure 8As shown, the AP can obtain the status of pin B of the MCU through the status of pin A, and then determine whether the MCU is accessing the eMMC; and, the MCU can obtain the status of pin A of the AP through the status of pin B, and then determine whether the AP is accessing the eMMC. Exemplarily, pin A or pin B can be a GPIO pin, etc., without specific limitation. When making a decision to access the eMMC based on whether the determined MCU processor is accessing the eMMC, the AP can write data to the eMMC, read data from the eMMC, or modify the data in the eMMC through input / output interface A; and, when making a decision to access the eMMC based on whether the determined AP processor is accessing the eMMC, the MCU can write data to the eMMC, read data from the eMMC, or modify the data A in the eMMC through input / output interface B. Exemplarily, input / output interface A or input / output interface B is an SDIO interface, etc., without specific limitation.

[0104] It should be noted that Figure 8 Only taking pin A as an example, which can be used both for the AP to obtain information on whether the MCU is accessing the eMMC and for indicating to other processors (such as the MCU) whether the AP is accessing the eMMC. However, the present application does not limit whether both are characterized by the status of the same pin. For example, in some embodiments, the AP may include a first pin and a third pin, where the first pin is used for the AP to obtain information on whether the MCU is accessing the eMMC, and the third pin is used to indicate to other processors (such as the MCU) whether the AP is accessing the eMMC.

[0105] Similarly, the MCU can obtain information on whether the AP is accessing the eMMC through pin B, and indicate whether the MCU is accessing the eMMC to other processors (such as the AP) through pin B. Or, in some embodiments, the MCU may include a second pin and a fourth pin, where the fourth pin is used for the MCU to obtain information on whether the AP is accessing the eMMC, and the second pin is used to indicate to other processors (such as the AP) whether the MCU is accessing the eMMC.

[0106] As an example, please refer to Figure 9 , Figure 9 Taking the example that the first processor and the second processor in the terminal device share the same memory, a flowchart of a method for accessing a memory provided by an embodiment of the present application is shown. As Figure 9 shown, this method can be implemented based on S901 - S903:

[0107] S901: The first processor receives a service request from an application, and the service request is used to request access to the memory.

[0108] Among them, the first processor can be any one of the multiple processors of the terminal device. For example, the first processor can be the main processor or the coprocessor. Taking a terminal device including an AP and an MCU as an example, the first processor can be the AP or the MCU.

[0109] In some embodiments, the service request can be a request initiated by an application in the first processor. As an example, the application can include, but is not limited to, any one or more of the following applications: music, heart rate, pedometer, sports health, music, sleep, watch face, etc. The embodiments of the present application do not make specific limitations, and can be determined according to the specific applications installed in the first processor, the specific functions of each application, and the specific usage scenarios, etc.

[0110] Taking the first processor being the AP as an example, the applications initiating the service request are such as music, watch face and other applications; taking the first processor being the MCU as an example, the applications initiating the service request are such as heart rate, pedometer, sports health, music, sleep, watch face and other applications.

[0111] In some embodiments, the purposes for the application to access the memory through the service request can include, but are not limited to, one or more of the following: reading data from the memory, writing data to the memory, modifying data in the memory. The embodiments of the present application do not make specific limitations, and can be determined according to the specific functions of the application and the specific usage scenarios, etc.

[0112] In some embodiments, the purposes for the application to access the memory through the service request can include, but are not limited to, accessing the partition corresponding to the first processor and not corresponding to the second processor (i.e., the exclusive partition of the first processor), and / or, the partition corresponding to the first processor and the second processor (i.e., the shared partition of the first processor and the second processor).

[0113] Among them, the exclusive partition of the first processor is used to store data from the first processor and can support the first processor to read the data stored in the exclusive partition of the first processor. The exclusive partition of the first processor cannot store data from other processors (such as the second processor) and cannot support other processors to read the data stored in the exclusive partition of the first processor. The shared partition can not only store data from the first processor and support the first processor to read the data stored in the shared partition, but also store data from other processors (such as the second processor) and support other processors to read the data stored in the shared partition.

[0114] In some embodiments, the memory may further include an exclusive partition for the second processor. The exclusive partition of the second processor is used to store data from the second processor and can support the second processor to read the data stored in the exclusive partition of the second processor. The exclusive partition of the second processor cannot store data from other processors (such as the first processor) and cannot support other processors to read the data stored in the exclusive partition of the second processor.

[0115] S902: The first processor obtains the situation of the second processor accessing the memory.

[0116] In some embodiments, the first processor may obtain second information, where the second information is used to characterize the situation of the second processor accessing the memory, such as whether the second processor is accessing the memory.

[0117] As a possible implementation, as Figure 9 shown, the first processor may obtain the situation of the second processor accessing the memory from the second processor, such as obtaining second information characterizing whether the second processor accesses the memory from the second processor.

[0118] As an example, the first processor includes a first pin, the second processor includes a second pin, the first pin is connected to the second pin, and the first processor can obtain the second information by obtaining the state of the first pin, that is, obtain whether the second processor is accessing the memory. The state of the first pin is used to characterize whether the second processor is accessing the memory. For example, the state of the first pin can be represented by a level, such as the state of the first pin includes a first level and a second level.

[0119] For example, if the state of the first pin is the first level, it is determined that the second processor is accessing the memory; if the state of the first pin is the second level, it is determined that the second processor is not accessing the memory. The first level is, for example, a high level, and the second level is, for example, a low level; or, the first level is a low level, and the second level is a high level, without specific limitation.

[0120] It can be understood that assuming the second processor does not access the memory, the second processor can set the state of the second pin to the fourth level. When the state of the second pin is at the fourth level, the state of the first pin of the first processor connected to the second pin is the second level. Based on this, if the state of the first pin is the second level, the first processor can determine that the state of the second pin is the fourth level and then determine that the second processor does not access the memory. Also, assuming the second processor is accessing the memory, the second processor can set the state of the second pin to the third level. When the state of the second pin is at the third level, the state of the first pin of the first processor connected to the second pin is the first level. Based on this, if the state of the first pin is the first level, the first processor can determine that the state of the second pin is the third level and then determine that the second processor is accessing the memory. Among them, the third level is, for example, a high level, and the fourth level is, for example, a low level; or the third level is a low level and the fourth level is a high level, which is not specifically limited.

[0121] As another possible implementation, the first processor can directly obtain whether other processors, such as other processors of a terminal device like the second processor, are accessing the memory from the storage driver of the other processors. The first processor can also obtain whether other processors are accessing the memory from other modules independent of the first processor and the second processor, such as a status storage unit.

[0122] As an example, as Figure 9 shown, a status storage unit can be included in the terminal device. The status storage unit is used to store status flag bits for each processor to access the memory, such as storing status flag bits for identifying whether each processor is accessing the memory. The first processor can obtain the situation of the second processor accessing the memory from the status storage unit, such as obtaining second information representing whether the second processor accesses the memory from the status storage unit.

[0123] For example, during the process that the second processor writes data to the memory or reads data from the memory in response to a service request of an application, a second flag can be saved in the status storage unit, where the second flag is used to identify that the second processor is accessing the memory. Based on this, during the process that the second processor accesses the memory, the first processor can obtain the status flag bit from the status storage unit and determine that the second processor is accessing the memory according to the status flag bit (such as the second identifier). Or, when the second processor accesses the memory, the second flag is not saved in the status storage unit to represent that the second processor does not access the memory. Based on this, the first processor can obtain the status flag bit from the status storage unit and determine that the second processor does not access the memory according to the status flag bit (such as not including the second identifier).

[0124] The embodiments of the present application do not specifically limit the specific manner and specific process of the first processor obtaining the situation of the second processor accessing the memory at S902.

[0125] In addition, the embodiments of the present application do not limit the specific form of the information used to characterize the situation of the second processor accessing the memory. For example, in some examples, the information (such as the second information) used to characterize the situation of the second processor accessing the memory may be in a plain text form such as direct indication; in other examples, the information (such as the second information) used to characterize the situation of the second processor accessing the memory may be in an implied form such as parameter characterization like level indication, or preset action (such as not replying) characterization. The embodiments of the present application do not specifically limit this.

[0126] In some embodiments, the execution result of S902 is that the second processor does not access the memory (such as the second information characterizes that the second processor does not access the memory). For this situation, the first processor executes Figure 9 the S903 shown.

[0127] S903: The first processor accesses the memory in response to a service request.

[0128] Among them, the specific operation of the first processor accessing the memory in response to a service request is related to the purpose of accessing the memory through the service request. For example, assuming that the purpose of the application accessing the memory through the service request is to read the first data in the memory, then the first processor reads the first data that the application wants to read from the memory in response to the service request. Another example, assuming that the purpose of the application accessing the memory through the service request is to write the second data to the memory, then the first processor writes the second data that the application wants to write to the memory in response to the service request. Another example, assuming that the purpose of the application accessing the memory through the service request is to modify the third data in the memory, then the first processor modifies the third data in the memory in response to the service request.

[0129] In some embodiments, the first processor can set the state of the third pin so that the state of the third pin is the fifth level when the first processor accesses the memory, where the state of the third pin being the fifth level is used to characterize that the first processor is accessing the memory. As a possible implementation, the first processor can adjust the state of the third pin from the sixth level to the fifth level after determining based on the execution result of S902 that the second processor does not access the memory and before the first processor accesses the memory, where the state of the third pin being the sixth level is used to characterize that the first processor does not access the memory. Based on this, it is convenient for other processors to know that the first processor is accessing the memory, so as to prevent conflicts caused by multiple processors accessing the memory simultaneously, and achieve a more scientific and orderly sharing of the memory.

[0130] In some embodiments, after S903 is executed, that is, after the first processor finishes accessing the memory, the first processor can reset the state of the third pin again so that the state of the third pin is the sixth level when the first processor does not access the memory. Based on this, it is convenient for other processors to know that the first processor does not access the memory, so as to realize a more scientific and orderly sharing of the memory.

[0131] In some embodiments, the execution result of S902 is that the second processor is accessing the memory (such as the second information indicates that the second processor is accessing the memory). For this situation, the first processor temporarily does not access the memory and obtains the situation of the second processor accessing the memory again after a period of time, and executes Figure 10 the S903 shown when the second processor does not access the memory. Among them, the first processor can Figure 10 obtain the situation of the second processor accessing the memory again through the

[0132] S1001: The first processor obtains the situation of the second processor accessing the memory.

[0133] In some embodiments, the first processor can obtain first information, where the first information is used to represent the situation of the second processor accessing the memory, such as whether the second processor is accessing the memory.

[0134] As a possible implementation manner, as Figure 10 shown, the first processor can obtain the situation of the second processor accessing the memory from the second processor, such as obtaining the first information representing whether the second processor accesses the memory from the second processor.

[0135] As an example, the first processor can obtain second information by obtaining the state of the first pin, that is, obtain whether the second processor is accessing the memory. For example, if the state of the first pin is the second level, the first processor can determine that the second processor does not access the memory; if the state of the first pin is the first level, the first processor can determine that the second processor is accessing the memory. Among them, the first level is such as a high level, and the second level is such as a low level; or, the first level is such as a low level, and the second level is such as a high level, which is not specifically limited.

[0136] As another possible implementation manner, as Figure 10 shown, the terminal device may include a status storage unit, and the status storage unit is used to store status flag bits of each processor accessing the memory, such as storing status flag bits for identifying whether each processor is accessing the memory. The first processor can obtain the situation of the second processor accessing the memory from the status storage unit, such as obtaining the first information representing whether the second processor accesses the memory from the status storage unit.

[0137] For example, if the status flag bit includes a second identifier, the first processor may determine that the second processor is accessing the memory; if the status flag bit does not include the second identifier, the first processor may determine that the second processor is not accessing the memory.

[0138] It should be noted that the embodiments of the present application do not limit the specific form of the information used to characterize the situation where the second processor accesses the memory. For example, in some examples, the information (such as the first information) used to characterize the situation where the second processor accesses the memory may be in a clear text form such as direct indication; in other examples, the information (such as the first information) used to characterize the situation where the second processor accesses the memory may be in an implied form such as parameter characterization like level indication or preset action (such as not replying) characterization. The embodiments of the present application do not make specific limitations.

[0139] As a possible implementation, if the execution result of S902 is that the second processor is accessing the memory (such as the second information characterizes that the second processor is accessing the memory), the first processor may temporarily not access the memory and periodically obtain the first information at a certain period T (such as every 100 milliseconds), for example, obtain the first information from the second processor or the status storage unit. Based on this, when the second processor finishes accessing the memory, the first processor can determine that the second processor is not accessing the memory based on the obtained first information, and then execute S903; or, when the second processor has not finished accessing the memory, the first processor determines that the second processor is accessing the memory based on the obtained first information and then continues to periodically obtain the first information from the second processor at the period T.

[0140] As another possible implementation, if the execution result of S902 is that the second processor is accessing the memory (such as the second information characterizes that the second processor is accessing the memory), the first processor may instruct the second processor to notify the first processor after finishing accessing the memory. For example, the first processor may enable the interrupt monitoring function, and after the interrupt monitoring function is enabled, the second processor actively notifies the first processor after finishing accessing the memory. It can be understood that compared with the implementation where the first processor periodically obtains the first information, this implementation can avoid the waste of power consumption and processing resources of the terminal device caused by the first processor continuously obtaining the first information.

[0141] As another possible implementation, if the execution result of S902 is that the second processor is accessing the memory (such as the second piece of information indicates that the second processor is accessing the memory), the first processor can wait for a period of time, such as waiting for a preset duration (such as 5 milliseconds), and then obtain the first piece of information, such as obtaining the first piece of information from the second processor or the status storage unit. Based on this, when the second processor finishes accessing the memory, the first processor can determine that the second processor is not accessing the memory based on the obtained first piece of information, and then execute S903; or, when the second processor has not finished accessing the memory, the first processor determines that the second processor is accessing the memory based on the obtained first piece of information, and then continues to periodically obtain the first piece of information from the second processor according to the period T. It can be understood that compared with the implementation where the first processor periodically obtains the first piece of information, this implementation can avoid the waste of power consumption and processing resources brought by the first processor continuously obtaining the first piece of information to the terminal device.

[0142] The present application embodiment does not specifically limit the specific manner and specific process for the first processor to obtain the situation of the second processor accessing the memory in S1001.

[0143] It should be noted that Figure 9 and Figure 10 Taking only the terminal device including the first processor and the second processor as an example, the present application embodiment does not limit the number of processors sharing the same memory in the terminal device. For example, in some embodiments, the terminal device includes a third processor different from the first processor and the second processor. In this case, in addition to obtaining the situation of the second processor accessing the memory, the first processor will also obtain the situation of the third processor accessing the memory. Further, when none of the other processors such as the second processor and the third processor are accessing the memory, the first processor executes Figure 9 the S903 shown, and when there is a processor among the other processors accessing the memory, the first processor does not access the memory temporarily until it determines that none of the other processors such as the second processor and the third processor are accessing the memory based on the execution result of Figure 10 the S1001 shown, and then executes Figure 10 the S903 shown.

[0144] As an example, please refer to Figure 11 , Figure 11 Taking the first processor accessing the memory as an example, a process flow chart of accessing the memory provided by the present application embodiment is shown. As Figure 11 shown, the process of accessing the memory may include S1101 - S1108:

[0145] S1101: The first processor receives a service request for accessing the memory.

[0146] Among them, the first processor can be any one of multiple processors of the terminal device. For example, the first processor can be the main processor or the coprocessor. Taking a terminal device including an AP and an MCU as an example, the first processor can be the AP or the MCU.

[0147] In some embodiments, the service request can be a request initiated by an application in the first processor, such as, but not limited to, any one or more of the following applications: music, heart rate, pedometer, sports health, music, sleep, watch face, etc.

[0148] In some embodiments, the purposes of the service requester can include, but are not limited to, one or more of the following: reading data from the memory, writing data to the memory, modifying data in the memory. The embodiments of the present application do not make specific limitations. For example, the purposes of the service requester can include, but are not limited to, one or more of the following: reading data in the exclusive partition of the first processor in the memory, reading data in the shared partition of the memory, writing data to the exclusive partition of the first processor in the memory, writing data to the shared partition of the memory, modifying data in the exclusive partition of the first processor in the memory, modifying data in the shared partition of the memory.

[0149] S1102: The first processor triggers a file operation.

[0150] As an example, the first processor triggers a file operation to trigger a specific access operation, such as writing, reading, etc.

[0151] As an example, if the purpose of the service request is reading, the first processor can trigger a read operation. For example, the first processor can call the read instruction; if the purpose of the service request is writing, the first processor can trigger a read-write operation. For example, the first processor can call the write instruction.

[0152] S1103: The first processor calls the storage driver.

[0153] As an example, the first processor calls the storage driver to obtain the situation of other processors (such as the second processor) accessing the memory.

[0154] In some embodiments, the storage driver of the first processor includes a first pin, and the state of the first pin is used to represent whether the memory (such as the second processor) connected to the second pin is accessing the memory. Based on this, the first processor can call the storage driver to obtain the state of the first pin, so as to obtain whether other processors (such as the second processor) are accessing the memory according to the state of the first pin.

[0155] As an example, the first pin or the second pin is, for example, a GPIO pin; of course, the first pin or the second pin can also be other pins, and the embodiments of the present application do not make specific limitations.

[0156] Of course, the embodiments of the present application do not limit the specific manner in which the first processor calls the storage driver to obtain the access of other processors (such as the second processor) to the memory. For example, in some embodiments, the first processor calls the storage driver to obtain a status flag bit from the status storage unit for characterizing whether other processors (such as the second processor) access the memory, so as to obtain whether other processors (such as the second processor) are accessing the memory according to the status flag bit.

[0157] The present application Figure 11 The example shown only takes the way that the first processor calls the storage driver to obtain the status of the first pin and obtains whether other processors are accessing the memory according to the status of the first pin as an example.

[0158] S1104: The first processor determines whether the status of the first pin is the second level.

[0159] As an example, if the status of the first pin is the first level, the first processor can determine that the status of the second pin is the third level and then determine that the second processor is accessing the memory; or, if the status of the first pin is the second level, the first processor can determine that the status of the second pin is the fourth level and then determine that the second processor is not accessing the memory.

[0160] As an example, the first level is, for example, a high level, and the second level is, for example, a low level; or, the first level is a low level and the second level is a high level.

[0161] As an example, the third level is, for example, a high level, and the fourth level is, for example, a low level; or, the fourth level is a low level and the third level is a high level.

[0162] In some examples, in S1104, the first processor determines that the status of the first pin is the second level, and then determines that the second processor is not accessing the memory. In this case, the first processor can normally access the memory. In order to facilitate other processors (such as the second processor) to know that the first processor is accessing the memory during the process of the first processor accessing the memory, the first processor can notify other processors (such as the second processor) of its memory access situation by setting the pin status. For example, when the first processor determines that the status of the first pin is the second level in S1104, the first processor executes the following S1105 - S1108:

[0163] S1105: The first processor sets the status of the third pin to the fifth level.

[0164] In some embodiments, a third pin is included on the storage drive of the first processor, and the state of the third pin is used to characterize the situation of the first processor accessing the memory, such as characterizing whether the first processor is accessing the memory. Based on this, the first processor can set the state of the third pin to a state indicating that the first processor is accessing the memory before accessing the memory.

[0165] As an example, the state of the third pin being at the sixth level is used to characterize that the first processor is not accessing the memory, and the state of the third pin being at the fifth level is used to characterize that the first processor is accessing the memory. Based on this, after determining that the second processor is not accessing the memory and before the first processor accesses the memory, the first processor can adjust the state of the third pin from the sixth level to the fifth level, so that other processors know that the first processor is accessing the memory, to prevent conflicts caused by multiple processors accessing the memory simultaneously, and to achieve a more scientific and orderly sharing of the memory.

[0166] S1106: The first processor determines whether the state of the first pin is at the second level.

[0167] In some embodiments, in order to avoid a conflict where the second processor starts accessing the memory after the first processor determines that the state of the first pin is at the second level based on S1104 and then determines that the second processor is not accessing the memory, resulting in the first and second processors accessing the memory simultaneously, the first processor can determine again whether the state of the first pin is at the second level to confirm again that the second processor is not accessing the memory.

[0168] S1107: The first processor accesses the memory.

[0169] Among them, the specific operation of the first processor accessing the memory in response to a service request is related to the purpose of accessing the memory through the service request by the application. For example, assuming that the purpose of the application accessing the memory through the service request is to read the first data in the memory, then the first processor reads the first data that the application wants to read from the memory in response to the service request. Another example, assuming that the purpose of the application accessing the memory through the service request is to write the second data to the memory, then the first processor writes the second data that the application wants to write to the memory in response to the service request. Another example, assuming that the purpose of the application accessing the memory through the service request is to modify the third data in the memory, then the first processor modifies the third data in the memory in response to the service request.

[0170] S1108: The first processor sets the state of the third pin to the sixth level.

[0171] Among them, the state of the third pin is the sixth level, which is used to represent that the first processor does not access the memory. Based on this, it is convenient for other processors to know that the first processor does not access the memory, so that other processors can access the memory in time when there is a need to access the memory, realizing a more scientific and orderly sharing of the memory.

[0172] It should be noted that the above embodiments only take the first processor determining that the state of the first pin is the second level based on S1104, and then determining that the second processor does not access the memory as an example. In other examples, as Figure 11 shown, if the first processor determines that the state of the first pin is not the second level based on S1104, such as the first level, the first processor can perform subsequent processing in any one of the following three ways (Way 1 - Way 3):

[0173] Way 1: Re - execute S1104, and execute S1105 - S1108 when the state of the first pin is the second level.

[0174] For example, the first processor can periodically execute S1104 at a certain period T (such as every 100 milliseconds) until it determines that the state of the first pin is the second level and then execute S1105 - S1108.

[0175] Based on this, the first processor can temporarily not access the memory, and re - execute S1104 to access the memory when ensuring that other second processors do not access the memory, so as to prevent conflicts caused by multiple processors accessing the memory simultaneously, realizing a more scientific and orderly sharing of the memory.

[0176] Way 2: Execute S1109 - S1110 and then re - execute S1104 - S1108.

[0177] Among them, S1109 - S1110 are as follows:

[0178] S1109: The first processor starts the interrupt monitoring function.

[0179] Among them, after the interrupt monitoring function is enabled, the second processor will actively notify the first processor after finishing accessing the memory. For example, after the second processor finishes accessing the memory, it can notify the first processor that the second processor has finished accessing the memory by adjusting the state of the second pin to the fourth level. Or, after the second processor finishes accessing the memory, it can notify the first processor that the second processor has finished accessing the memory by sending a reminder or other means. The embodiments of the present application do not limit the specific means.

[0180] S1110: The interrupt detection function indicates that the state of the first pin is the second level.

[0181] Based on this, the first processor can temporarily refrain from accessing the memory and, by activating the interrupt monitoring function, access the memory again when ensuring that other second processors are not accessing the memory. While promptly responding to service requests to access the memory, it prevents conflicts caused by multiple processors accessing the memory simultaneously, achieving a more scientific and orderly sharing of the memory.

[0182] Moreover, compared with Method 1, Method 2 can avoid waste of power consumption, processing resources, etc. of the terminal device caused by the first processor continuously obtaining the situation of the second processor accessing the memory.

[0183] Method 3: After executing S1111 - S1112, re - execute S1104 - S1108.

[0184] Among them, S1111 - S1112 are specifically as follows:

[0185] S1111: The first processor starts the waiting time.

[0186] Exemplarily, the waiting time is, for example, waiting for a preset duration, such as waiting for 5 milliseconds.

[0187] S1112: Wait for more than the preset duration.

[0188] Based on this, the first processor can temporarily refrain from accessing the memory and, by waiting for more than the preset duration and then making another judgment, access the memory again when ensuring that other second processors are not accessing the memory, so as to prevent conflicts caused by multiple processors accessing the memory simultaneously, achieving a more scientific and orderly sharing of the memory.

[0189] Moreover, compared with Method 1, Method 3 can avoid waste of power consumption, processing resources, etc. of the terminal device caused by the first processor continuously obtaining the situation of the second processor accessing the memory.

[0190] In addition, it should be noted that the above - mentioned embodiments only take the first processor determining that the state of the first pin is the second level based on S1106 and then determining that the second processor is not accessing the memory as an example. In some other examples, such as Figure 11 shown, if the first processor determines that the state of the first pin is not the second level but the first level based on S1106, then the first processor can also adopt any one of the above - mentioned Method 1 - Method 3 for subsequent processing, which will not be repeated here.

[0191] It can be understood that based on the method for accessing the memory provided in this application, such as Figure 9 and Figure 10The method of accessing a memory as shown. Multiple processors (such as a first processor and a second processor) of a terminal device can ensure that any processor can normally perform data storage, modification, or reading of stored data, etc. in any usage scenario by sharing the same memory. For example, compared with the architecture where an MCU stores MCU-related data in the memory configured for an AP, even when the AP and the memory configured for the AP are powered off in the low-power mode, the storage of MCU-related data and the normal reading, modification, deletion, etc. of the stored data can still be carried out normally. Also, any one of the multiple processors (such as the first processor) can implement mutually exclusive access to the memory by multiple processors based on the situation of other processors accessing the memory, such as whether other processors are accessing the memory, to achieve a more scientific and orderly sharing of the memory.

[0192] Also, the solution where multiple processors (such as a first processor and a second processor) of the terminal device provided in this application share the same memory can also reduce the production cost of the terminal device and support the miniaturization of the terminal device.

[0193] In addition, since multiple processors (such as a first processor and a second processor) of the terminal device share the same memory, when a certain processor writes a certain data (such as the data of Music A) to the memory, other processors can know that the data has been written to the memory. Then, when other processors receive a service request to write the same data to the memory, the processor can no longer repeat writing the same data but can normally feedback a successful writing message to the application. Based on this, the problem of some data related to applications related to multiple processors (such as an AP and an MCU) being repeatedly written can be avoided.

[0194] The embodiments of this application do not limit the specific processing method adopted by the first processor when it determines that the state of the first pin is not the second level based on S1104. The first processor can adopt any of the above methods 1 - 3 for subsequent processing; and the embodiments of this application do not limit the specific processing method adopted by the first processor when it determines that the state of the first pin is not the second level based on S1106. The first processor can adopt any of the above methods 1 - 3 for subsequent processing, depending on specific device capabilities, power consumption requirements, service requirements, usage scenarios, etc.

[0195] In addition, it should be noted that the above embodiments only take the example that the first processor executes S1106 after executing S1105, and then executes S1107-S1108 based on the execution result of S1106, or executes S1107-S1108 after executing S1109-S1110 based on the execution result of S1106, or executes S1107-S1108 after executing S1111-S1112 based on the execution result of S1106. This application does not limit whether the first processor executes S1106 after executing S1105. That is to say, S1106 is not an essential step. For example, in some embodiments, after executing S1105, the first processor may directly execute S1107-S1108.

[0196] It should be understood that the various solutions of the embodiments of the present application can be combined and used reasonably, and the explanations or descriptions of the various terms appearing in the embodiments can be referred to or explained with each other in the various embodiments, which are not limited herein.

[0197] It should also be understood that in the various embodiments of the present application, the magnitudes of the sequence numbers of the above processes do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0198] It can be understood that in order to implement the functions of any of the above embodiments, a terminal device, etc. includes the corresponding hardware structure and / or software module for executing each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of the examples described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described function for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0199] Embodiments of the present application can divide functional modules for a terminal device, etc. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical function division, and there can be other division methods in actual implementation. It should also be understood that each module in the terminal device, etc. can be implemented in the form of software and / or hardware, and no specific limitation is made thereto. In other words, the terminal device, etc. is presented in the form of functional modules. Here, the "module" can refer to an application specific integrated circuit (ASIC), a circuit, a processor and a memory that execute one or more software or firmware programs, an integrated logic circuit, and / or other devices that can provide the above functions.

[0200] In an alternative manner, when software is used to implement data transmission, it can be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are implemented in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital video disk (DVD)), or a semiconductor medium (such as a solid state disk (SSD)).

[0201] The steps of the method or algorithm described in connection with the embodiments of the present application may be implemented in hardware or by a processor executing software instructions. The software instructions may be composed of corresponding software modules, and the software modules may be stored in a random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) memory, register, hard disk, removable hard disk, compact disc read-only memory (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and the storage medium may be located in an application specific integrated circuit (ASIC). Additionally, the ASIC may be located in a terminal device. Of course, the processor and the storage medium may also exist as discrete components.

[0202] Through the description of the above embodiments, those skilled in the art can clearly understand that for the convenience and simplicity of description, only the above division of each functional module is used as an example. In actual applications, the above functions may be allocated to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above.

Claims

1. A method for accessing a memory, characterized in that, The method is applied to a first processor in a terminal device. The terminal device further includes a second processor and a memory, and the first processor and the second processor share the memory. The method includes: Receiving a service request of an application, where the service request is used to request access to the memory; Obtaining first information from the second processor, where the first information is used to characterize whether the second processor is accessing the memory; When the first information characterizes that the second processor is not accessing the memory, accessing the memory in response to the service request.

2. The method according to claim 1, wherein The first processor includes a first pin, and the first pin is connected to a second pin of the second processor. The obtaining the first information from the second processor includes: Obtaining the state of the first pin, where the state of the first pin is used to characterize whether the second processor is accessing the memory.

3. The method according to claim 2, wherein The state of the first pin includes a first level and a second level. The method further includes: If the state of the first pin is the first level, determining that the second processor is accessing the memory; If the state of the first pin is the second level, determining that the second processor is not accessing the memory.

4. The method according to claim 3, wherein When the state of the second pin is a third level, the state of the first pin is the first level; When the state of the second pin is a fourth level, the state of the first pin is the second level.

5. The method according to any one of claims 1 to 4, characterized in that, The first processor further includes a third pin, and the state of the third pin characterizes whether the first processor is accessing the memory.

6. The method according to claim 5, wherein When the first processor accesses the memory, the state of the third pin is a fifth level; when the first processor does not access the memory, the state of the third pin is a sixth level.

7. The method according to claim 6, characterized in that The method further includes: Before the first processor accesses the memory, adjusting the state of the third pin from the sixth level to the fifth level.

8. The method according to claim 7, characterized in that, The adjusting the state of the third pin from the sixth level to the fifth level includes: After receiving the service request, obtaining second information from the second processor, where the second information is used to characterize whether the second processor accesses the memory; When the second information characterizes that the second processor is not accessing the memory, adjusting the state of the third pin from the sixth level to the fifth level.

9. The method according to claim 8, wherein The obtaining the first information from the second processor includes: When the second information characterizes that the second processor is accessing the memory, waiting for a preset duration and then obtaining the first information from the second processor.

10. The method according to any one of claims 1-9, characterized in that, The service request is used to request access to one or more of the following partitions in the memory: a partition corresponding to the first processor and not corresponding to the second processor, a partition corresponding to both the first processor and the second processor.

11. The method according to claim 10, wherein The memory further includes a partition corresponding to the second processor and not corresponding to the first processor.

12. The method according to any one of claims 1-11, wherein the first processor accesses the memory for performing one or more of the following: reading data from the memory, writing data to the memory, and modifying data in the memory.

13. The method according to any one of claims 1-12, wherein the first processor is an application processor AP, and the second processor is a microprogram controller MCU; or, the first processor is an MCU, and the second processor is an AP; wherein, the memory is an embedded multimedia card eMMC.

14. A chip, characterized in that, The chip includes: a processing module and one or more pins, and the processing module and the one or more pins are used to support the chip to implement the method according to any one of claims 1-13.

15. A terminal device, characterized in that, The terminal device includes: a first processor, a second processor, and a memory, the first processor and the second processor share the memory, and the first processor or the second processor is used to implement the method according to any one of claims 1-13.

16. A computer-readable storage medium, characterized in that, Computer program instructions are stored on the computer-readable storage medium, and when the computer program instructions are executed by a processing circuit, the method according to any one of claims 1-13 is implemented.

17. A computer program product containing instructions, characterized in that, When the computer program product runs on a computer, the computer is caused to execute the method according to any one of claims 1-13.

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