Data processing method and device, electronic equipment and storage medium
By dividing the cache into regions within a multi-core processor, important threads can prioritize using the larger cache region, thus resolving the issue of multiple processes competing for shared cache resources. This improves data access speed and application response speed, enhancing the user experience.
Patent Information
- Application Number
- CN202410502206.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-24
- Publication Date
- 2025-10-24
AI Technical Summary
In multi-core processors, the problem of multiple processes preempting or competing for shared cache resources slows down the acquisition of important process data, affecting application response speed and user experience.
By dividing the processor's shared cache into different regions, important threads can preferentially use the cache region with larger storage space, while non-important threads can use the cache region or memory with smaller storage space. This isolates the cache data storage regions for different thread types, thus achieving cache resource skew.
Improved data access speed for important threads, ensuring smooth and stable application operation and enhancing user experience.
Smart Images
Figure CN120832228A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of computer, and particularly relates to a data processing method and device, electronic equipment and storage medium. BACKGROUND
[0002] A processor cache is composed of a group of cache memories on a processor chip, and is used to store data and instructions recently used by the processor. In order to facilitate management and utilization of the cache, the cache is usually divided into multiple levels, and the capacity and speed of each level of cache are different. The closer to the processor, the faster the speed and the smaller the capacity of the cache, and the farther away from the processor, the slower the speed and the larger the capacity of the cache. In a multi-core processor, the cache farthest from the processor is a shared cache shared by multiple processor cores. Therefore, reasonable allocation of resources of the shared cache is the key to improving the performance and efficiency of the multi-core processor. SUMMARY
[0003] To overcome the problems in the related art, the present disclosure provides a data processing method and device, electronic equipment and storage medium.
[0004] According to a first aspect of an embodiment of the present disclosure, a data processing method is provided, and the method comprises:
[0005] If the target thread is an important thread, the first cache area is used as a target storage area;
[0006] If the target thread is a non-important thread, the second cache area is used as the target storage area;
[0007] The cache data of the target thread is stored in the target storage area, or the cache data of the target thread is read from the target storage area;
[0008] The first cache area and the second cache area are part of storage areas in a processor shared cache, and the first cache area is larger than the second cache area; or the first cache area is all storage areas in the processor shared cache, and the second cache area is a storage area in a memory.
[0009] In an exemplary embodiment, the method further comprises:
[0010] According to the function of the target thread, a thread type of the target thread is determined.
[0011] In an exemplary embodiment, the determination of the thread type of the target thread according to the function of the target thread comprises:
[0012] According to the function of the target thread, a thread identification of the target thread is determined.
[0013] determining a thread type of the target thread according to the thread identification.
[0014] In an example embodiment, the determining the thread identification of the target thread according to the function of the target thread comprises:
[0015] if the target thread is a foreground thread or a display thread or a critical task thread, determining the thread identification of the target thread as a first set value;
[0016] if the target thread is a background thread or a non-critical task thread, determining the thread identification of the target thread as a second set value.
[0017] In an example embodiment, the method further comprises:
[0018] modifying the thread identification of the target thread when the function of the target thread changes.
[0019] In an example embodiment, the determining the thread type of the target thread according to the thread identification comprises:
[0020] if the thread identification of the target thread is the first set value, determining the target thread as an important thread;
[0021] if the thread identification of the target thread is the second set value, determining the target thread as a non-important thread.
[0022] In an example embodiment, the storing the cache data of the target thread in the target storage area comprises:
[0023] storing the cache data of the target thread in the target storage area when the target thread is executed for the first time;
[0024] the reading the cache data of the target thread from the target storage area comprises:
[0025] reading the cache data of the target thread from the target storage area when the thread type of the target thread does not change and the target thread is not executed for the first time.
[0026] According to a second aspect of the embodiments of the present disclosure, a data processing apparatus is provided, and the apparatus comprises:
[0027] a determining module configured to determine a first cache area as a target storage area if a target thread is an important thread, and determine a second cache area as the target storage area if the target thread is a non-important thread;
[0028] a processing module configured to store cache data of the target thread in the target storage area, or read the cache data of the target thread from the target storage area;
[0029] The first cache area and the second cache area are part of a processor shared cache, and the first cache area is larger than the second cache area; or the first cache area is the entire storage area in the processor shared cache, and the second cache area is a storage area in a memory.
[0030] According to a third aspect of the embodiments of the present disclosure, an electronic device is provided, comprising:
[0031] a processor;
[0032] a memory for storing processor-executable instructions;
[0033] The processor is configured to perform the method as described in the first aspect of the embodiments of the present disclosure.
[0034] According to a fourth aspect of the embodiments of the present disclosure, a non-transitory computer-readable storage medium is provided, when instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as described in the first aspect of the embodiments of the present disclosure.
[0035] The above method of the present disclosure has the following beneficial effects: by classifying threads according to importance, and isolating cache data storage areas between different thread types, the cache resources are tilted, the data access speed of important threads is improved, the performance and response speed of important threads are improved, the application program runs smoothly and stably, and the user experience is improved.
[0036] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS
[0037] The accompanying drawings, which are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.
[0038] Figure 1 is a flowchart of a data processing method according to an exemplary embodiment;
[0039] Figure 2 is a flowchart of a data processing method according to an exemplary embodiment;
[0040] Figure 3 is a flowchart of a data processing method according to an exemplary embodiment;
[0041] Figure 4 is a schematic diagram of a target storage area according to an example embodiment;
[0042] Figure 5 is a schematic diagram of a target storage area according to an example embodiment;
[0043] Figure 6 is a block diagram of a data processing apparatus according to an example embodiment;
[0044] Figure 7 is a block diagram of an electronic device according to an example embodiment. DETAILED DESCRIPTION
[0045] The example embodiments will be described in detail herein with reference to the attached drawings. The following description is made with reference to the accompanying drawings, in which like reference numerals represent like elements, unless otherwise indicated. The following description of example embodiments is not representative of all embodiments consistent with the present disclosure. Rather, it is merely an example of apparatus and methods consistent with some aspects of the present disclosure as detailed in the appended claims.
[0046] A processor cache speeds up the operation of a computer and improves the performance of a computer by storing the most frequently used data or instructions inside the processor, thereby reducing the number of accesses to the main memory. A processor cache is usually divided into multiple levels, which balances the speed of data access and the use of limited cache resources as much as possible. In some embodiments, in a multi-core processor, the processor cache hierarchy includes a level 1 cache (L1 cache), a level 2 cache (L2 cache), and a level 3 cache (L3 cache), wherein each processor core corresponds to a dedicated L1 cache and an L2 cache, and the L3 cache is a shared cache shared by multiple processor cores. Therefore, the size and resource allocation of the L3 cache affect the cache hit rate and performance between multiple processor cores.
[0047] In the related art, when multiple processes are executed simultaneously, the shared cache is shared by multiple processor cores, and the problem of contention for the shared cache resources between multiple processes occurs, resulting in important processes being unable to quickly obtain data. For example, a foreground process stores data accessed last time in the processor shared cache, but as data of other background processes is stored subsequently, the data stored by the foreground process is overwritten by the data of other background processes, resulting in the foreground process needing to obtain data from the main memory again when accessing data next time, so that the foreground process obtains data slowly, the application program responds slowly and runs stably, and the user experience is affected.
[0048] In an example embodiment of the present disclosure, in order to overcome the problem of contention for the shared cache resources between multiple processes in the related art, a data processing method is provided, including: if the target thread is an important thread, taking the first cache area as the target storage area; if the target thread is a non-important thread, taking the second cache area as the target storage area; storing the cache data of the target thread in the target storage area, or reading the cache data of the target thread from the target storage area; wherein the first cache area and the second cache area are part of the storage areas in the processor shared cache, and the first cache area is larger than the second cache area; or the first cache area is all the storage areas in the processor shared cache, and the second cache area is a storage area in the memory. The method classifies threads according to importance, and isolates the cache data storage areas between different thread types, realizes the inclination of cache resources, can improve the data access speed of important threads, improve the performance and response speed of important threads, ensure the smooth and stable running of the application program, and improve the user experience.
[0049] In an example embodiment of the present disclosure, a data processing method is provided, Figure 1 is a flowchart of a data processing method according to an example embodiment, as shown in Figure 1 , including the following steps:
[0050] Step S101, if the target thread is an important thread, taking the first cache area as the target storage area;
[0051] Step S102, if the target thread is a non-important thread, taking the second cache area as the target storage area;
[0052] Step S103, storing the cache data of the target thread in the target storage area, or reading the cache data of the target thread from the target storage area.
[0053] The data processing method in the embodiment of the present disclosure is applied to electronic devices, including mobile phones, tablets, personal computers, smart wearable devices, smart car machines and other electronic devices with multi-core processors.
[0054] In step S101 and step S102, the target thread is any thread currently to be executed by the processor, the data accessed in executing the target thread is the cache data of the target thread, the cache data is stored in the processor cache (Cache), and the cache data can be quickly read in the next execution of the target thread, so as to improve the data access speed of the target thread. When storing the cache data of the target thread, the cache data is preferentially stored in the processor private cache corresponding to the target thread, i.e. the L1 cache and the L2 cache; since the space of the L1 cache and the L2 cache is small, when the storage space thereof is insufficient, the cache data is stored in the processor shared cache, i.e. the L3 cache; when the storage space of the processor shared cache is insufficient, the cache data is stored in the memory, i.e. the main memory.
[0055] The thread type of the target thread is determined, and the thread type includes important threads and non-important threads. The thread type is divided according to user demand, and the threads with high user demand are important threads, and other threads are non-important threads. When the target thread is executed, the thread type of the target thread is determined, and the target storage area is determined according to the thread type of the target thread. The target storage area includes the processor shared cache and the memory. In order to avoid the occupation or contention of the processor shared cache between different threads, and the interference of the data storage or reading of the important threads by the non-important threads, the use of the processor shared cache is controlled by software, so that the target storage areas used by threads of different thread types are different. For example, the correspondence between the thread type and the target storage area is set in the controller in advance, and after the thread type of the currently executed thread is determined, the target storage area is determined according to the correspondence.
[0056] If the target thread is an important thread, the first cache area is used as the target storage area; if the target thread is a non-important thread, the second cache area is used as the target storage area. The first cache area and the second cache area are divided in the following two ways:
[0057] The first way is that the first cache area and the second cache area are part of the storage areas in the processor shared cache, and the first cache area is larger than the second cache area.
[0058] The storage area in the processor shared cache is divided into a first cache area and a second cache area by CPBM (CPU Performance Monitoring), and the storage area with larger storage space is taken as the target storage area of the important thread, and the storage area with smaller storage space is taken as the target storage area of the unimportant thread. For example, the size of the L3 cache is 12 MB, which is divided into a first cache area and a second cache area, with sizes of 10 MB and 2 MB respectively, the first cache area is the target storage area of the important thread, and the second cache area is the target storage area of the unimportant thread.
[0059] Secondly, the first cache area is all the storage areas in the processor shared cache, and the second cache area is the storage area in the memory.
[0060] All the storage areas in the processor shared cache are taken as the first cache area, that is, the important thread exclusively occupies the processor shared cache, and the memory is taken as the second cache area, that is, the unimportant thread does not occupy the processor shared cache. The memory is the main memory, for example, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory).
[0061] In step S103, the cache data of the target thread is stored in the target storage area, and if the thread type of the target thread does not change, the cache data is read from the target storage area when the target thread is executed again next time. If the target thread is an important thread, the data reading speed when executed next time can be ensured, so that the response speed of the application program is ensured; if the target thread is an unimportant thread, the data storage and data reading of the important thread will not be disturbed.
[0062] In some embodiments, when the target thread is executed for the first time, the cache data of the target thread is stored in the target storage area, and when the thread type of the target thread does not change and the target thread is executed for the first time, the cache data of the target thread is read from the target storage area. Since the target storage area changes when the thread type changes, after it is determined that the target thread is an important thread or an unimportant thread, the cache data is stored in the target storage area when the target thread is executed for the first time under the thread type, and the cache data can be directly read when executed next time.
[0063] In the example embodiment of the present disclosure, according to the thread type of the target thread, the target storage area is determined, if the target thread is an important thread, the first cache area is taken as the target storage area, if the target thread is a non-important thread, the second cache area is taken as the target storage area, the cache data of the target thread is stored in the target storage area, or the cache data of the target thread is read from the target storage area, wherein the thread type includes important threads and non-important threads, and the target storage areas of different thread types are different. This method classifies threads by importance, isolates the cache data storage areas between different thread types, realizes the inclination of cache resources, can improve the data access speed of important threads, improve the performance and response speed of important threads, ensure the smooth and stable running of application programs, and improve the user experience.
[0064] In the example embodiment of the present disclosure, a data processing method is provided, Figure 2 is a flow chart of a data processing method according to an example embodiment, as shown in Figure 2 comprises the following steps:
[0065] Step S201, according to the function of the target thread, the thread type of the target thread is determined;
[0066] Step S202, if the target thread is an important thread, the first cache area is taken as the target storage area;
[0067] Step S203, if the target thread is a non-important thread, the second cache area is taken as the target storage area;
[0068] Step S204, the cache data of the target thread is stored in the target storage area, or the cache data of the target thread is read from the target storage area.
[0069] The specific implementation of steps S202-S204 can refer to steps S101-S103, and will not be repeated here.
[0070] In step S201, when the target thread is executed, the function of the target thread is determined, the thread type of the target thread is determined according to the function of the target thread, threads of different functions correspond to different thread types, threads that can directly affect the user's fluency experience are divided into important threads, and other threads are divided into non-important threads. The function of the thread includes foreground thread, background thread, display thread, critical task thread, non-critical task thread, etc. When the target thread is a foreground thread or a display thread or other critical task thread, the data acquisition speed of the target thread will directly affect the user's fluency experience, and when the target thread is a background thread or a non-critical task thread, the data acquisition speed of the target thread will not directly affect the user's fluency experience. Therefore, the foreground thread or the display thread or the other critical task thread is divided into the important thread, and the background thread or the non-critical task thread is divided into the non-important thread. The display thread includes a foreground graphics rendering thread, i.e., a UX (User Experience) display thread, and the critical task thread includes a derivative thread of the foreground thread.
[0071] In some embodiments, according to the function of the target thread, the thread identification of the target thread is determined; and according to the thread identification, the thread type of the target thread is determined.
[0072] The function of each thread is determined, threads with different functions are distinguished by thread identification, and the thread identification of each thread is written into the MPAM (Memory System Resource Partitioning and Monitoring) register of the corresponding processor. The MPAM register determines the thread type according to the thread identification, and determines the corresponding target storage area according to the thread type. The MPAM register is used to store the cache data of the thread to the target storage area. When the target thread is executed, the thread identification of the target thread is determined according to the function of the target thread, and is written into the MPAM register of the processor corresponding to the target thread. The MPAM register stores the cache data of the target thread to the target storage area according to the thread identification of the target thread.
[0073] In an example, if the target thread is a foreground thread or a display thread or a critical task thread, the thread identification of the target thread is determined as a first set value; and if the target thread is a background thread or a non-critical task thread, the thread identification of the target thread is determined as a second set value.
[0074] The first set value can be a single numerical value, and the foreground thread or the display thread or the critical task thread is uniformly set to the same value; or the first set value can be multiple numerical values, and the foreground thread, the display thread and the critical task thread correspondingly set different values. The second set value is a single numerical value. The first set value is different from the second set value.
[0075] In an example, if the thread identification of the target thread is a first set value, the target thread is determined as an important thread; if the thread identification of the target thread is a second set value, the target thread is determined as a non-important thread.
[0076] If the thread identification of the target thread stored in the MPAM register is a first set value, the target thread is determined as an important thread; if the thread identification of the target thread stored in the MPAM register is a second set value, the target thread is determined as a non-important thread.
[0077] In some embodiments, the thread identification of the target thread is modified when the function of the target thread changes.
[0078] When the target thread is switched from a foreground thread to a background thread, or from a background thread to a foreground thread, the function of the target thread changes, and the importance also changes. At this time, the thread identification of the target thread is switched, and the switched thread identification is written into the MPAM register again to overwrite the thread identification before the switch.
[0079] In the embodiment, the thread type is determined according to the function of the thread, the important threads can be divided more targetedly, and the shared cache of the processor can be utilized to the greatest extent.
[0080] In an example embodiment of the present disclosure, a data processing method is provided, Figure 3 is a flow diagram of a data processing method according to an example embodiment, as shown in Figure 3 includes the following steps:
[0081] Step S3-1, in the initialization stage, a default thread identification is set for each thread, denoted as Partid.
[0082] For example, the default thread identification is 16, and the default thread identification of each thread is set by the command "task_struct->partid===16".
[0083] Step S3-2, when the target thread is switched to a foreground thread, the thread identification of the target thread is modified to a first value in the first set value.
[0084] For example, the first value is 17, and the thread identification of the target thread is set by the command "task_struct->partid===17".
[0085] Step S3-3, when the target thread is a display thread, the thread identification of the target thread is modified to a second value in the first set value.
[0086] For example, the second value is 18, and the thread identifier of the target thread is set by the command "task_struct->partid == 18".
[0087] Step S3-4, when the target thread is a critical task thread, the thread identifier of the target thread is modified to the third value in the first set value.
[0088] For example, the critical task thread is a derived thread of the target thread, and the third value is 19, and the thread identifier of the target thread is set by the command "task_struct->partid == 19".
[0089] Step S3-5, the thread identifier of the target thread is written into the MPAP register of the processor corresponding to the target thread.
[0090] Step S3-6, the MPAP register determines the target storage area according to the thread identifier of the target thread, and stores the cache data of the target thread in the target storage area, or reads the cache data of the target thread from the target storage area.
[0091] In an example, Figure 4 and Figure 5 respectively show the schematic diagram of the target storage area in two different cases, and the currently executed threads include the foreground thread on CPU0, the display thread on CPU1, the background thread 1 on CPU2, and the background thread 2 on CPU3. As shown in Figure 4 , the L3 Cache (i.e. L3 level cache) is divided into a first cache area and a second cache area, and the first cache area is larger than the second cache area, wherein the foreground thread and the display thread use the first cache area after using their respective exclusive caches (i.e. L1 level cache and L2 level cache), and the background thread 1 and the background thread 2 use the second cache area after using their respective exclusive caches, and the above four threads use DDR after using the L3 Cache; as shown in Figure 5 , the foreground thread and the display thread exclusively use the L3 Cache after using their respective exclusive caches, and use DDR after using the L3 Cache, and the background thread 1 and the background thread 2 directly use DDR after using their respective exclusive caches.
[0092] By using the data processing method in the above embodiment, the system performance of the electronic device can be improved in the following aspects:
[0093] I. Smoothness improvement, during system running, the inclination of cache resources to important threads can improve the smoothness score of a single application by 2.4%;
[0094] II. Cache Miss Reduction. In the case where the CPU, GPU, and DDR frequencies are fixed and the heat, which may affect performance, is turned off, the cache miss rate of a key process of an application during sliding is counted. The cache miss rate is reduced from 10.89% to 9.98% before and after the data processing method in the embodiments of the present disclosure is used.
[0095] III. Score of a Specific Item. In the case where the Antutu tool is used to test a specific item of a Debug APK at room temperature, the MEM (Memory) is improved by 0.78%.
[0096] An example embodiment of the present disclosure provides a data processing apparatus, Figure 6 FIG. 1 is a block diagram of a data processing apparatus according to an example embodiment. Figure 6 As shown in FIG. 1, the data processing apparatus includes:
[0097] The determining module 601 is configured to, if the target thread is an important thread, take the first cache region as the target storage region; and if the target thread is a non-important thread, take the second cache region as the target storage region.
[0098] The processing module 602 is configured to store the cache data of the target thread in the target storage region, or read the cache data of the target thread from the target storage region.
[0099] The first cache region and the second cache region are part of the storage region in the processor shared cache, and the first cache region is larger than the second cache region; or the first cache region is the entire storage region in the processor shared cache, and the second cache region is the storage region in the memory.
[0100] In an example embodiment, the determining module 601 is further configured to:
[0101] If the target thread is an important thread, the first cache region is taken as the target storage region.
[0102] If the target thread is a non-important thread, the second cache region is taken as the target storage region.
[0103] The first cache region and the second cache region are part of the storage region in the processor shared cache, and the first cache region is larger than the second cache region; or the first cache region is the entire storage region in the processor shared cache, and the second cache region is the storage region in the memory.
[0104] In an example embodiment, the determining module 601 is further configured to:
[0105] According to the function of the target thread, the thread type of the target thread is determined.
[0106] In an example embodiment, the determining module 601 is further configured to:
[0107] determine the thread identification of the target thread according to the function of the target thread;
[0108] determine the thread type of the target thread according to the thread identification.
[0109] In an example embodiment, the determining module 601 is further configured to:
[0110] if the target thread is a foreground thread or a display thread or a critical task thread, determine the thread identification of the target thread as a first set value;
[0111] if the target thread is a background thread or a non-critical task thread, determine the thread identification of the target thread as a second set value.
[0112] In an example embodiment, the determining module 601 is further configured to:
[0113] modify the thread identification of the target thread when the function of the target thread changes.
[0114] In an example embodiment, the determining module 601 is further configured to:
[0115] if the thread identification of the target thread is the first set value, determine the target thread as an important thread;
[0116] if the thread identification of the target thread is the second set value, determine the target thread as a non-important thread.
[0117] In an example embodiment, the processing module 602 is further configured to:
[0118] when the target thread is executed for the first time, store the cache data of the target thread in the target storage area;
[0119] the processing module 602 is further configured to:
[0120] when the thread type of the target thread does not change and the target thread is not executed for the first time, read the cache data of the target thread from the target storage area.
[0121] As to the apparatus in the above-mentioned embodiments, the specific manners in which various modules perform operations have been described in detail in the embodiments related to the method, and thus will not be described in detail here.
[0122] Figure 7 is a block diagram of an electronic device 700 according to an example embodiment.
[0123] Referring to Figure 7The electronic device 700 can include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, a multimedia component 708, an audio component 710, an input / output (I / O) interface 712, a sensor component 714, and a communication component 716.
[0124] The processing component 702 usually controls overall operations of the electronic device 700, such as operations associated with displaying, making phone calls, data communications, camera operations, and recording operations. The processing component 702 can include one or more processors 720 to execute instructions to complete all or part of steps of the above methods. In addition, the processing component 702 can include one or more modules to facilitate the interaction between the processing component 702 and other components. For example, the processing component 702 can include a multimedia module to facilitate the interaction between the multimedia component 708 and the processing component 702.
[0125] The memory 704 is configured to store various types of data to support operations of the electronic device 700. Examples of these data include instructions for any application or method operating on the electronic device 700, contact data, phonebook data, messages, pictures, videos, and the like. The memory 704 can be implemented by any type of volatile or non-volatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.
[0126] The power supply component 706 provides power for the various components of the electronic device 700. The power supply component 706 can include a power supply management system, one or more power supplies, and other components associated with generating, managing and distributing power for the electronic device 700.
[0127] The multimedia component 708 includes a screen to provide an output interface between the electronic device 700 and a user. In some embodiments, the screen can include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive an input signal from a user. The touch panel includes one or more touch sensors to sense a touch, a slide, and a gesture on the touch panel. The touch sensor can not only sense a boundary of a touching or a sliding action, but also detect duration and intensity of the touching or sliding action. In some embodiments, the multimedia component 708 includes a front camera and / or a rear camera. When the electronic device 700 is in an operating mode, such as a camera mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have a focal length and optical zooming capability.
[0128] The audio component 710 is configured to output and / or input an audio signal. For example, the audio component 710 includes a microphone (MIC) to receive an external audio signal when the electronic device 700 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 704 or transmitted via the communication component 716. In some embodiments, the audio component 710 also includes a speaker to output an audio signal.
[0129] The I / O interface 712 provides an interface for the processing component 702 and peripheral interface modules, which can be a keypad, a click wheel, buttons, and the like. The buttons can include, but are not limited to, a home button, a volume button, a start button, and a lock button.
[0130] The sensor component 714 includes one or more sensors to provide various state assessments for the electronic device 700. For example, the sensor component 714 can detect an open / closed state of the electronic device 700, relative positioning of components, such as a display and a keypad of the electronic device 700, a change in position of the electronic device 700 or a component of the electronic device 700, presence or absence of user contact with the electronic device 700, an orientation or acceleration / deceleration of the electronic device 700, and a temperature change of the electronic device 700. The sensor component 714 can include a proximity sensor to detect presence of an object in proximity to the electronic device 700 without any physical contact. The sensor component 714 can also include a light sensor, such as a CMOS or CCD image sensor, to use in an imaging application. In some embodiments, the sensor component 714 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.
[0131] The communication component 716 is configured to facilitate wired or wireless communication between the electronic device 700 and other devices. The electronic device 700 can access a wireless network based on a communication standard, such as WiFi, 2G, or 3G, or a combination thereof. In an exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 further includes a Near Field Communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on Radio Frequency Identification (RFID) techniques, infrared data association (IrDA) techniques, ultra-wideband (UWB) techniques, Bluetooth (BT) techniques, and other techniques.
[0132] In an exemplary embodiment, the electronic device 700 can be implemented with one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic elements, for performing the above-described methods.
[0133] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions, such as the memory 704 including instructions, is also provided, which can be executed by the processor 720 of the electronic device 700 to complete the above-described methods. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disc, and an optical data storage device, etc.
[0134] A non-transitory computer-readable storage medium, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform a data processing method, the method including any one of the above-described methods.
[0135] Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
[0136] It is to be understood that the present disclosure is not limited to the precise construction described and as shown in the attached drawings, and that various modifications and changes can be effected therein by those skilled in the art without departing from the scope of the disclosure. The scope of the disclosure is to be limited only by the appended claims.
Claims
1. A data processing method, characterized by, The method comprises: if the target thread is an important thread, taking the first cache region as a target storage region; if the target thread is a non-important thread, taking the second cache region as the target storage region; storing cache data of the target thread in the target storage region, or reading the cache data of the target thread from the target storage region; wherein the first cache region and the second cache region are partial storage regions in a processor shared cache, and the first cache region is larger than the second cache region; or the first cache region is the entire storage region in the processor shared cache, and the second cache region is a storage region in a memory.
2. The method of claim 1, wherein, The method further comprises: determining a thread type of the target thread according to a function of the target thread.
3. The method of claim 2, wherein, The determining of the thread type of the target thread according to the function of the target thread comprises: determining a thread identification of the target thread according to the function of the target thread; determining the thread type of the target thread according to the thread identification.
4. The method of claim 3, wherein, The determining of the thread identification of the target thread according to the function of the target thread comprises: if the target thread is a foreground thread or a display thread or a critical task thread, determining the thread identification of the target thread as a first set value; if the target thread is a background thread or a non-critical task thread, determining the thread identification of the target thread as a second set value.
5. The method of claim 4, wherein, The method further comprises: modifying the thread identification of the target thread when the function of the target thread changes.
6. The method of claim 4, wherein, The determining of the thread type of the target thread according to the thread identification comprises: if the thread identification of the target thread is the first set value, determining the target thread as an important thread; if the thread identification of the target thread is the second set value, determining the target thread as a non-important thread.
7. The method of claim 1, wherein, The storing of the cache data of the target thread in the target storage region comprises: when the target thread is executed for the first time, storing the cache data of the target thread in the target storage region. The reading of the cache data of the target thread from the target storage region comprises: when the thread type of the target thread does not change and the target thread is not executed for the first time, reading the cache data of the target thread from the target storage region.
8. A data processing apparatus, characterized by, The apparatus comprises: a determining module configured to, if a target thread is an important thread, take a first cache region as a target storage region, and if the target thread is a non-important thread, take a second cache region as the target storage region; a processing module configured to store cache data of the target thread in the target storage region, or read the cache data of the target thread from the target storage region; wherein the first cache region and the second cache region are partial storage regions in a processor shared cache, and the first cache region is larger than the second cache region; or the first cache region is the entire storage region in the processor shared cache, and the second cache region is a storage region in a memory.
9. An electronic device, comprising: comprise: a processor; a memory for storing processor-executable instructions; The processor is configured to perform the method of any one of claims 1-7.
10. A non-transitory computer-readable storage medium, comprising: When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is enabled to perform the method of any one of claims 1-7.