Method for establishing access by fusing multiple levels of cache directories

A technology for caching directories and establishing methods, which is applied in memory systems, memory address/allocation/relocation, instruments, etc. It can solve the problems of no shared CPUCache and GPUCache, no expansion of heterogeneous thousand-core systems, etc., and achieve good system compatibility , good scalability, and the effect of reducing failure rate

Inactive Publication Date: 2014-07-30
UNIV OF SHANGHAI FOR SCI & TECH
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Problems solved by technology

Hechtman et al. proposed a Cache coherence mechanism based on shared virtual memory for heterogeneous multi-core systems. thousand-core system

Method used

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  • Method for establishing access by fusing multiple levels of cache directories

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Embodiment Construction

[0013] The basic composition of the hierarchical cache directory mechanism of hierarchical fusion is to design the Cuckoo directory within the Quart level, cache the data blocks of the isomorphic CPU computing core or GPU computing core, and take advantage of the advantages of the Cuckoo directory occupying a small cache area and low power consumption. Since 64 Quarts share a high-speed crossover bus in the heterogeneous thousand-core processor architecture, the communication load on the bus is heavy, and the arbitration conflict of communication will increase sharply. Therefore, designing the region directory (Region Directory) outside the Quart level can not only effectively reduce the communication bandwidth of the bus, reduce the frequency of arbitration conflicts, but also cache the data block directory of the three-level fusion cache and improve the access hit rate of the three-level fusion cache. Therefore, it is planned to build a hierarchical Cache directory mechanism ...

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Abstract

The invention relates to a method for establishing an access by fusing multiple levels of cache directories, and a graded fused hierarchical cache directory mechanism is established. The method comprising the steps that multiple CPU and GPU processors form a Quart computing element, a Cuckoo directory is established in a graded way in caches built in the CPU or GPU processors, an area directory and an area directory controller are established outside the Quart computing element, thus the bus communication bandwidth is effectively reduced, the arbitration conflict frequency is lowered, a data block directory of a three-level fusion Cache can be cached, and thus the access hit rate of the three-level fusion Cache is improved. Therefore a graded fused hierarchical Cache directory mechanism inside and outside the Quart is constructed, the Cache failure rate is lowered, the on-chip bus bandwidth is reduced, the power consumption of the system is lowered, the new status of the Cache block does not need to be added, the very good compatibility with the Cache consistency protocol is realized, and a new train of thought is provided for constructing a heterogeneous monolithic multi-core processor system with extensibility and high performance.

Description

technical field [0001] The invention relates to a computer cache technology, in particular to a method for establishing and accessing an integrated multi-level cache directory. Background technique [0002] The cache (Cache) directory and its consistency mechanism are key technologies in many-core processor storage systems. In the past three years, the research on the Cache directory and its consistency mechanism of the heterogeneous many-core system has been active in the world. Protoza is an adaptive granularity cache coherence mechanism, which achieves effective spatial locality by avoiding wasted communication bandwidth and unnecessary coherence traffic. SPATL separates the shared mode from the Bloom filter and uses a tagless Cache directory mechanism to eliminate redundant copies. The scalable consistency directory proposed by Sanchez et al. for 1024-core single-chip multiprocessors, but the directory mechanism is only a single-level Cache directory, and needs to trac...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F12/0811G06F12/0817
CPCY02D10/00
Inventor 裴颂文
Owner UNIV OF SHANGHAI FOR SCI & TECH
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