Explicit multi-core Cache consistency active management method facing flow application

Abstract

Disclosed is an explicit multi-core Cache consistency active management method facing flow application. The method comprises the steps that private data Cache set an optional total state descriptor and a shared data function digit of an identification Cache to the read-write state of shared data; the total state descriptor is used for identifying the operational state of the whole private data Cache to the shared data currently, Y groups are configured according to the number requirement for simultaneous locking of the Cache, the feature information of each locking area is stored in each group, and a shared address section or locking sign information can be achieved; the shared data function digit is a two-dimensional array register, the width is N, and the depth is M; the N is used for distinguishing N different locking shared data areas corresponding to lines or blocks of the Cache, and the M is the same as the number of the lines or the blocks of the private data Cache to identify the corresponding lines or the blocks of the Cache to determine whether the shared data need to be read and written or not. The explicit multi-core Cache consistency active management method facing the flow application has the advantages of being simple in principle, convenient to operate, small in price for hardware implementation, good in expandability, strong in configurability, capable of improving system efficiency and the like.

Description

technical field [0001] The present invention mainly relates to the field of Cache consistency implementation strategy and method design in single-chip multi-core microprocessors, in particular refers to a single-core proprietary Data Cache is an active management method that maintains the consistency of shared storage data. Background technique [0002] With the continuous development of the computer application field, a typical data-intensive application - stream application, is becoming an important load of multi-core processors. Streaming applications are mainly divided into two categories: one is media applications, such as real-time digital signal processing applications such as audio, video, encoding and decoding in the fields of wireless communication and image processing; the other is scientific computing, which is mainly used for high-precision science Modeling, typical applications include fluid mechanics, molecular dynamics, finite element analysis, biotechnology...

AI Technical Summary

Problems solved by technology

As the number of processor cores increases, the broadcast monitoring protocol has the following problems: (1) With the increase of processor cores, the interconnection hardware overhead of inter-core broadcast increases, and the line delay is huge; (2) each The private data cache of a single core needs to monitor broadcasts from all other cores, which is interfered by too many monitoring transactions; the benefits of using Cache are offset

[0008] (1) A large number of broadcast requests to maintain data consistency lead to tight inter-core communication bandwidth, increased data transmission pressure, and increased control complexity;

[0009] (2) The blindness of broadcast requests can easily lead to unreasonable waste of system resources

When multiple cores execute different tasks in parallel, in most cases there are a considerable number of irrelevant cores that do not need to receive and process a broadcast request to maintain consistency from other cores, and these consistency maintenance transactions will interrupt the normal processing that is running tasks; therefore, the broadcasting method used in the traditional architecture to maintain consistency has brought unnecessary waste to system resources; and has greatly reduced computing performance;

[0010] (3) The core that performs the lock write operation can release the write lock only when its broadcast invalidation request is received by all other cores and the operation is completed. The unforeseen additional delay brought by the multi-core processing process increases the difficulty of programming for programmers ;Releasing the write lock after the broadcast is completed can alleviate a small amount, but it will bring new consistency problems;

[0011] (4) The processing time required by the receiver to process consistency maintenance transactions from other cores is lengthy

When processing a larger region-based request, the obsolete data block will contain multiple Cahce lines, and the entire processing time is unacceptable;

[0012] (5) The private data cache in the core needs a dedicated address calculation and comparison structure in order to handle invalidation requests. At the same time, considering the multi-core communication overhead, a large buffer structure and a dedicated communication control module are also required, resulting in a complex design of the private data cache controller and an area of , high power consumption overhead

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