Cache consistency protocol verification method and system for on-chip multi-core processor, and medium

Abstract

The invention discloses a Cache consistency protocol verification method and system for an on-chip multi-core processor, and a medium. The method comprises the steps of loading and executing a test program for the on-chip multi-core processor executing a Cache protocol to be verified, tracking a Cache related message of an on-chip network, and recording the life cycle of a Cache transaction through a recording board file; checking whether the running result of the test program has an error or not, if so, judging that the Cache protocol verification does not pass the test, and exiting; otherwise, checking an error scene in the execution process of the record board file positioning test program, and if the error scene is found or the record board file still has an unfinished Cache transaction, judging that the Cache protocol verification does not pass the test; otherwise, judging that the Cache protocol verification passes the test. According to the invention, an error scene can be accurately positioned in a verification process, and design vulnerabilities and errors are easy to discover.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to an on-chip multi-core processor Cache (high-speed buffer) consistency protocol verification method, system and medium. Background technique [0002] With the development of integrated circuit technology, multi-core and many-core processors have become a development trend. Multi-core processors (Chip Multi-processor, CMP) have been widely used in high-performance servers, online transaction processing and other fields. As the demand for data communication between multi-core and multi-thread continues to increase, it is necessary to integrate a large-capacity Cache on-chip to realize data sharing and information interaction, thereby reducing memory access latency and access conflicts. On-chip multi-core structure has become the mainstream technology of current high-performance microprocessors. The implementation of cache coherence protocol is also closely related to on-c...

AI Technical Summary

Problems solved by technology

[0004] The traditional test program is a random test program or application program. The advantage of the traditional test is that the programmer does not need to consider the Cache protocol, but the memory access mode may be single, and the correctness of the protocol cannot be fully tested. The traditional test is not completely aimed at the Cache protocol. The test, so the efficiency is not high, and it is difficult to locate after the data error is found

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