Cache consistency protocol verification method and system for on-chip multi-core processor, and medium

A multi-core processor and verification method technology, which is applied in the field of Cache (cache) consistency protocol verification of on-chip multi-core processors, can solve the problems of inability to fully test the correctness of the protocol, difficult positioning, and low efficiency, and achieves easy detection of design errors. , the effect of accurately locating the wrong scene

Active Publication Date: 2020-09-01
NAT UNIV OF DEFENSE TECH
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0004] The traditional test program is a random test program or application program. The advantage of the traditional test is that the programmer does not need to consider the Cache protocol, but the memory access mode may be sing

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  • Cache consistency protocol verification method and system for on-chip multi-core processor, and medium
  • Cache consistency protocol verification method and system for on-chip multi-core processor, and medium
  • Cache consistency protocol verification method and system for on-chip multi-core processor, and medium

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Embodiment Construction

[0032] In order to make the content of the present invention more clear and understandable, the content of the present invention will be described in detail below in conjunction with specific embodiments of the present invention and accompanying drawings.

[0033] like figure 1 As shown, the steps of the on-chip multi-core processor Cache consistency protocol verification method in this embodiment include:

[0034] 1) Load and execute the test program for the on-chip multi-core processor that executes the Cache protocol to be verified, and track the Cache-related messages of the on-chip network, and record the life cycle of the Cache transaction through the record board file;

[0035]2) Check whether there is an error in the running result of the test program. The error means that the memory access data read by the read request for the same memory access address is inconsistent with the memory access data written by the last write request of the memory access address, or the ...

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Abstract

The invention discloses a Cache consistency protocol verification method and system for an on-chip multi-core processor, and a medium. The method comprises the steps of loading and executing a test program for the on-chip multi-core processor executing a Cache protocol to be verified, tracking a Cache related message of an on-chip network, and recording the life cycle of a Cache transaction through a recording board file; checking whether the running result of the test program has an error or not, if so, judging that the Cache protocol verification does not pass the test, and exiting; otherwise, checking an error scene in the execution process of the record board file positioning test program, and if the error scene is found or the record board file still has an unfinished Cache transaction, judging that the Cache protocol verification does not pass the test; otherwise, judging that the Cache protocol verification passes the test. According to the invention, an error scene can be accurately positioned in a verification process, and design vulnerabilities and errors are easy to discover.

Description

technical field [0001] The present invention relates to the field of computer technology, in particular to an on-chip multi-core processor Cache (high-speed buffer) consistency protocol verification method, system and medium. Background technique [0002] With the development of integrated circuit technology, multi-core and many-core processors have become a development trend. Multi-core processors (Chip Multi-processor, CMP) have been widely used in high-performance servers, online transaction processing and other fields. As the demand for data communication between multi-core and multi-thread continues to increase, it is necessary to integrate a large-capacity Cache on-chip to realize data sharing and information interaction, thereby reducing memory access latency and access conflicts. On-chip multi-core structure has become the mainstream technology of current high-performance microprocessors. The implementation of cache coherence protocol is also closely related to on-c...

Claims

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Application Information

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IPC IPC(8): G06F11/22
CPCG06F11/2242G06F11/2273G06F11/2268Y02D10/00
Inventor 罗莉周理潘国腾荀长庆冯权友周海亮铁俊波欧国东王蕾龚锐石伟任巨
Owner NAT UNIV OF DEFENSE TECH
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