Replacement method for Cache row in LLC

A priority and target technology, applied in the computer field, can solve problems such as reducing cache access performance, and achieve the effect of improving access performance and reducing invalidation

Active Publication Date: 2014-11-26
INSPUR BEIJING ELECTRONICS INFORMATION IND
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the data block is frequently accessed in the upper cache, the above invalid operations will greatly reduce the cache access performance

Method used

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  • Replacement method for Cache row in LLC
  • Replacement method for Cache row in LLC
  • Replacement method for Cache row in LLC

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Embodiment Construction

[0020] The present invention will be further described in detail below in conjunction with the accompanying drawings. These implementation examples are described in sufficient detail to enable those skilled in the art to practice the invention. Logical, implementation and other changes may be made in the implementation without departing from the spirit and scope of the invention.

[0021] figure 1 It is a structural schematic diagram of the multi-core shared Cache processor of the present invention. like figure 1 As shown, the Cache processor has two levels of Cache, the L1 close to the processor core is the upper level Cache, and the LLC far away from the processor core is the lower level Cache. L1 and LLC have an inclusion relationship, that is, the cache line of L1 has a copy in LLC, but the cache line of LLC does not necessarily have a copy in L1, and the operation of the cache line cannot destroy the inclusion relationship. In addition, L1 is private to the processor ...

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Abstract

The invention provides a replacement method for a Cache row in a last level cache (LLC). If a target Cache address is lost in the LLC, the replacement priority of a Cache row which is recently called in is calculated according to the operation type, the original Cache row with the highest replacement priority is replaced according to the replacement priority orderly principle, and the Cache row which is recently called in is stored to the corresponding position of the target Cache; if the target Cache address is in the LLC, the replacement priority of the current access Cache row is updated according to the Cache consistency state and operation type, and the priority of the current access Cache row is upgraded or degraded according to the replacement priority orderly principle. Performance losses caused by inclusive victims led into the inclusive Cache in a replacement mode can be effectively reduced.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a method for replacing Cache lines in a last level cache memory (LLC, Last Level Cache). Background technique [0002] In order to fill the performance gap between processors and storage systems, modern processors usually use a multi-layer Cache structure. Among them, an important design scheme is to include a Cache (Inclusive Cache) hierarchical structure design. In the Inclusive Cache hierarchy, the Cache lines of the upper-level Cache close to the processor core have copies in the lower-level Cache far away from the processor core, while the Cache lines in the lower-level Cache do not necessarily have copies in the upper-level Cache. This structure Can simplify the Cache coherency protocol. However, inclusive caches may suffer a performance penalty compared to non-inclusive and exclusive cache structures. On the one hand, due to the repeated storage of data, the effective...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F12/0806G06F12/0842G06F12/123
Inventor 王恩东倪璠陈继承
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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