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Cache consistency protocol-free distributed sharing on-chip storage framework

A storage architecture and distributed technology, applied in the field of processors, can solve the problems of complex judgment and high communication overhead, and achieve the effect of avoiding the cache coherence protocol and reducing the cache miss rate.

Active Publication Date: 2015-12-23
FUDAN UNIV
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage is that the judgment is complicated and the communication overhead is large

Method used

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  • Cache consistency protocol-free distributed sharing on-chip storage framework
  • Cache consistency protocol-free distributed sharing on-chip storage framework
  • Cache consistency protocol-free distributed sharing on-chip storage framework

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Embodiment Construction

[0025] First, the program is compiled into machine code by a compiler. Among them, the generated static initialization data and other shared data will be placed in such as image 3 A non-cached block in L1 memory is shown. Others are placed in the corresponding main memory block, and the address codes of the two are continuous, which is convenient for the programming model.

[0026] Such as figure 1 As shown, taking a cluster containing 4 processors as an example, the 4 main memory blocks #0, #1, #2, #3 are respectively distributed in the four processors #0, #1, #2, #3 Private area (other processors in the cluster cannot directly access memory), thus forming a distributed storage architecture.

[0027] Such as figure 2 As shown, each processor in the cluster is also equipped with a local shared cache. In the figure, the local shared cache#x only maps the main memory block #x (that is, local), and can be shared and accessed by all other processors in the cluster in the cl...

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Abstract

The invention belongs to the technical field of processors and particularly relates to a cache consistency protocol-free distributed sharing on-chip storage framework. According to the framework, a cache is only mapped to a local primary memory space based on a cluster structure, and a processor finishes reading and writing of other shared primary memory blocks in a cluster by accessing to caches of other cores, so that overlapped primary memory address spaces are no longer mapped among the caches of different cores, and the cache consistency problem of a multi-core processor is solved; and an L1 storage device of a local core is divided into two parts, i.e., a non cache storage device and the cache, so that the cache miss rate is reduced and corresponding complicated logic circuits and power consumption are avoided. Moreover, a direct memory access (DMA) operation is supported, i.e., DMA is supported in a stream application to directly perform inter-cluster large data transit on a primary memory, so that the framework is suitable for large-scale expansion.

Description

technical field [0001] The invention belongs to the technical field of processors, and in particular relates to a distributed shared on-chip storage structure without a cache consistency protocol. Background technique [0002] In recent years, multi-core processors have been widely favored by the industry due to their inherent parallelism and excellent energy efficiency. Multi-core processors generally adopt a shared storage architecture design, and low latency, high bandwidth, and large capacity storage architectures are the key goals of the design. [0003] In order to have both the large capacity of the main memory and the high speed of the on-chip memory, the memory hierarchy is generally introduced, and the main memory data is mapped to the cache (super high-speed cache) by using the locality principle of the memory access data, and the processor directly links it to the High-speed reading and writing. [0004] In the storage hierarchy of existing multi-core processor...

Claims

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Application Information

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IPC IPC(8): G06F12/08
CPCY02D10/00
Inventor 荆明娥周力君田书东谢志成尹颖颖王洁琳杨建伟
Owner FUDAN UNIV
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