Constant Cache capable of supporting pipeline operation

Abstract

The invention relates to the technical field of computer hardware, in particular to a constant Cache capable of supporting pipeline operation. The constant Cache comprises a PLRU algorithm module 2, alabel control module 1, an FIFO module 3 and a memory module 4. The PLRU algorithm module 2 is used for generating a Cache block address to be updated according to historical access information of each Cache block and sending the Cache block address to the label control module 1; the label control module 1 is used for determining whether or not a current cache request is hit, and sending a judgment result to the PLRU algorithm module 2, and if the current cache request is hit, data mapped to the constant Cache by a memory is directly read from the memory module 4 and sent back to a request initiator; if the current cache request is not hit, a parameter address is buffered to the FIFO module 3, the data is written into the memory module 4 according to the Cache block address to be updatedafter the data is retrieved from the memory, the parameter address is read out from the FIFO module 3 and processing is conducted; the FIFO module 3 is used for storing a parameter address which is not hit; the memory module 4 is used for storing the data mapped to the constant Cache to wait for reading after the constant Cache is hit.

Description

technical field [0001] The invention relates to the technical field of computer hardware, in particular to a constant Cache supporting pipelining. Background technique [0002] With the rapid development of computer systems, modern computer systems are increasingly limited by the performance of the main memory. The performance of the processor is increasing at a rate of 60% per year, while the bandwidth of the main memory chip is only increasing at a rate of 10% per year. In terms of speed, the gap between main memory and processor has always been about an order of magnitude. As the speed gap between CPU and memory is getting bigger and bigger, Cache appears, which is between CPU and main memory. Its access speed is close to CPU speed, but its capacity is small and its price is high. [0003] The emergence of Cache is a helpless compromise and has become one of the key factors affecting system performance. Embedded systems are now becoming an important part of the compute...

AI Technical Summary

Problems solved by technology

If the data accessed once hits in the cache, it only takes 1 or 2 processor cycles to get the data; but if the required data is not in the cache, it often takes an order of magnitude more processor cycles to get the data

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