Heterogeneous platform based multi-parallel error detection system framework

A technology of error detection and architecture, applied in the fields of instruments, electrical digital data processing, computers, etc., can solve the problems of idle computing units, unreasonable use of shared resources, etc., and achieve the effect of small running overhead

Inactive Publication Date: 2015-12-02
FUDAN UNIV
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Problems solved by technology

Also, these computing units are often idle while programmers are debugging
On the other hand, although parallel errors have different manifestations, they are essentially caused by unreasonable use of shared resources.
Therefore, the focus of the program state required for detection is on the memory access records (especially the shared memory access records), which makes the detection process somewhat similar in terms of front-end collection

Method used

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  • Heterogeneous platform based multi-parallel error detection system framework
  • Heterogeneous platform based multi-parallel error detection system framework
  • Heterogeneous platform based multi-parallel error detection system framework

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Embodiment Construction

[0021] The technology in the present invention will be described in detail below in conjunction with the description of the drawings and the pseudo code of the algorithm. The invention mainly utilizes the powerful parallel computing ability and programmability of the graphic processor in the heterogeneous platform. Collect memory access records on the general processor side, send the records to the graphics processor side through the on-chip interconnection bus, and finally perform error detection on the graphics processor side. On this basis, the present invention utilizes: (1) Utilize Bloom filter to filter secure memory access records; (2) Avoid shared memory access from being replaced; (3) "Last write" identification simplifies detection work, these three optimization strategies Improve detection speed and detection accuracy.

[0022] 1. Implementation of heterogeneous platforms required for multiple parallel error detection

[0023] First, in order to improve universa...

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Abstract

The invention belongs to the technical field of parallel processors and particularly relates to a heterogeneous platform based multi-parallel error detection system framework. According to the framework, powerful parallel computing capability and programmability of a universal graphic processor in a heterogeneous platform are mainly utilized to simultaneously detect mainstream multiple parallel errors, including data competition, atomic contravention and sequential contravention. In the aspect of design complexity, only relatively smooth hardware complexity is required, the logic of an on-chip key path (such as high-speed cache or cache consistency) does not need to be changed, only a memory access collection module and a memory access preprocessing module are added for collecting memory access instructions possibly causing the parallel errors and providing related information of error detection separately, and an error detection algorithm realizes high parallelism by utilizing the universal graphic processor. The hardware framework provided by the invention can discover the parallel errors in the program running process and is very low in runtime overhead.

Description

technical field [0001] The invention belongs to the technical field of parallel processors, and in particular relates to a variety of parallel error detection architectures based on the processing capabilities of heterogeneous platforms (combined architectures of general-purpose processors and graphics processors). Background technique [0002] With the development of computer technology, multi-core processors are becoming more and more common. In daily life, desktops, laptops, tablets, and even mobile phones are already equipped with multi-core processors. The increase in the number of processor cores on a single chip brings potential computing power. In order to take full advantage of computing resources on multi-core devices, parallel programs are commonly used. However, writing correct parallel programs is not easy due to parallel program bugs. On the one hand, programmers are accustomed to the serialized way of thinking, which leads to errors when writing parallel pr...

Claims

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Application Information

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IPC IPC(8): G06F15/163G06F15/167
Inventor 张为华余时强
Owner FUDAN UNIV
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