Semiconductor device and method for testing the same

Abstract

A semiconductor device wherein a simple circuit arrangement is used to shorten the test time and suppress increase of circuit area required for the test. The semiconductor device (10) has a micro-memory (11) consolidated with a logic part. The micro-memory (11) includes an operation control circuit (12) for executing data read/write operations in accordance with input signals including addresses, data and commands. A storage area of the micro-memory (11) that is selected by an address includes a test register (16) for storing data used for selecting a test mode. A write circuit (15) produces, in response to a write command supplied from the operation control circuit (12), a control signal (RGT) for permitting an operation of writing data into the test register (16).

Description

technical field [0001] The present invention relates to a semiconductor device in which a logic unit and a memory unit are mixed and an inspection method thereof. Background technique [0002] Patent Document 1 JP-A-10-65104 (FIG. 12) [0003] Patent Document 2 JP-A-11-250700 [0004] Patent Document 3 JP-A-2000-57120 [0005] In recent years, semiconductor devices (LSI), such as ASICs and microprocessors, have become highly integrated, and micro memories (storage units) and logic units have begun to be mixed together. Memory mixed LSIs are subject to operational inspection before shipment. This operational inspection tests whether the logic part and micromemory are operating normally. A technique that shortens the inspection time of micromemory with a simple circuit structure is required. [0006] In the mixed memory LSI, normal operations (write operation and read operation) in the micro memory are controlled by signals from the logic unit. For example, when a read com...

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Problems solved by technology

Therefore, there is a problem that the circuit area increases and the die size of the LSI increases.

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