201 results about "Tests times" patented technology

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The invention provides a double-station radio frequency chip high-low temperature high-speed test sorting machine which comprises a test assembly, and the test assembly comprises a shell, a workbench, a preprocessor, a first air inlet pipe, a first exhaust pipe, a placing device and a detection table; the inner side wall of the shell is fixedly connected with a workbench, two preprocessors are symmetrically installed on the top of the workbench, the outer side walls of the preprocessors communicate with an air inlet pipe and an exhaust pipe, and the top of the workbench is symmetrically and fixedly connected with two detection tables. The chip is preprocessed through the preprocessor, it is ensured that the chip reaches the required test temperature before entering the detection table, and therefore the overall test time is shortened. The test cover slidably connected to the test bench facilitates rapid replacement of the test chip, and further improves the test speed. By adding the double testing stations, testing can be carried out alternately, two groups of chips can be tested at the same time, the waiting time is shortened, and the testing efficiency is improved.

The invention relates to a TSN network minimization intrusive test scheduling method for guaranteeing production safety priority, which comprises the following steps: step 1, reservation of time-space isolated test resources: distributing a special test time slot with the lowest priority for test flow in a scheduling period of a centralized network controller; and step 2, a dynamic detection strategy of service awareness: monitoring key performance indexes of the key production service queue in real time, and when all the key performance indexes are lower than a preset threshold value, injecting test flow in a test time slot. And step 3, adaptive network optimization of closed loop feedback. According to the invention, on the premise of not influencing the normal operation of the key production service under the coal mine, the accurate and real-time monitoring of the TSN network state can be realized, the non-inductive test effect of the service is finally achieved, and the self-adaptive optimization capability is realized.

The invention relates to the technical field of chip function testing, and particularly discloses a multi-site testing method for TOF sensor chip function testing, which comprises the following steps: completing hardware self-inspection and software loading; the host receives a'ready 'signal fed back by the sorting machine / probe station through GPIB communication, and confirms that each slave and the corresponding peripheral are in a'to-be-tested' state through TCP communication or Pipe interaction; the host issues an independent test instruction to each slave; after each slave receives the instruction, the corresponding test resource board card is controlled to provide a test condition for the chip to be tested, and the chip output data is collected at the same time; after completing the single-station test, each slave uploads a test result to the host; the host captures the test data from the corresponding network disk and counts the yield; and the host sends the final result of the multi-station test to the sorting machine / probe station through the communication driver and automatically grabs the next batch of chips to be tested. According to the method, the overall test time is greatly shortened through the multi-site parallel test.

The invention provides an enhancement method for a question answering system during testing based on reinforcement learning, and belongs to the technical field of natural language processing. The method aims at solving the technical problems that an existing large language model (LLM) faces knowledge blind areas, reasoning chain breakage and context length limitation in a question and answer (QA) task, an existing fine adjustment method is high in calculation cost and damaged in generalization ability, and a prompt strategy seriously depends on a limited context window and lacks long-term memory. The method comprises the following steps: firstly, collecting reflection experience through multiple attempts and a failure reflection mechanism, and constructing an experience library; thirdly, performing text embedding, clustering and semantic abstracting on experiences in the experience library, and constructing an external memory library; secondly, a memory selection process is formalized into a Markov decision process (MDP), reinforcement learning (such as a PPO algorithm) is used for training a strategy agent, and the agent is optimized with a current task as a state, with memory item selection as an action and with LLM answer correctness as a reward; finally, in a test time (inference) phase, the agent dynamically selects the most helpful memory entry according to the new task and integrates it into the hint of the LLM to generate a final answer. According to the method, under the condition that LLM internal parameters do not need to be updated, the question and answer accuracy is dynamically improved, the calculation overhead is reduced, and the limitation of a context window is effectively overcome.

This invention discloses a shoe wear simulation test circuit and method. The shoe wear simulation test circuit includes at least an EBS controller, and the shoe wear simulation test method includes: acquiring the current test voltage, providing the current test voltage to the EBS controller, and receiving the current feedback signal output by the EBS controller; determining the current theoretical remaining wear of the shoe based on the current test voltage; determining the current tested remaining wear of the shoe based on the current feedback signal; and determining the current test result based on the current theoretical remaining wear and the current tested remaining wear. The technical solution of this invention can realize the simulation test of shoe wear detection function in a laboratory environment, with short test time and high accuracy, thus improving the reliability and safety of the braking system.

The application provides a press-pack IGBT sub-module test adapter and a test device. The press-pack IGBT sub-module test adapter comprises a lower clamp. The lower clamp comprises: a conductive base plate, the conductive base plate having an array of positioning holes, the array of positioning holes comprising a plurality of separate positioning holes; a positioning assembly, the positioning assembly comprising a conductive adapter, the conductive adapter being adapted to be placed on the array of positioning holes, the conductive adapter being provided with a first recess, the first recess being adapted to place a to-be-tested sub-module; and a first fastener, the first fastener being adapted to penetrate the conductive adapter on the side of the first recess and extend in at least part of the positioning holes. When the structure of the to-be-tested sub-module changes, the structure of the whole adapter does not need to be redesigned, the universality of the adapter is improved, and thus the test cost is reduced and the test time is shortened.

The application belongs to the technical field of automatic test program, and particularly relates to a LabVIEW test method of a multi-channel programmable output clock buffer. The method comprises the following steps: initializing the clock buffer after power-on; resetting the FSWP spectrum analyzer and clearing the previous interface settings; switching the radio frequency switch to channel 1 and opening the channel 1 output; setting the signal source input frequency; setting the signal source input amplitude; starting the signal source input, and outputting the set frequency and amplitude to the input end of the clock buffer; starting the register configuration module, and transmitting the 174 24-bit register values to the SPI in sequence through the serial port, and then transmitting the SPI to the clock buffer; reading the data on the FSWP spectrum analyzer; and the method automatically measures the key indicators of the 14-channel clock buffer, saves the data and judges the advantages and disadvantages. The method reduces the burden of the test personnel, reduces the test time cost, and avoids causing data errors.

The invention discloses a CAN routing test function implementation method, device and equipment and a storage medium, and the method comprises the steps: obtaining original CAN data through collection, carrying out the preprocessing of the original CAN data, and obtaining the preprocessed target CAN data; extracting key information of a routing message from the target CAN data, and obtaining difference data according to the key information; the difference data is displayed through the display module, multiple CAN channels can be tested, the testing method is friendly, the automation degree is high, compatibility is high, the testing efficiency can be greatly improved, automatic testing is achieved, the accuracy of testing routes under the condition of multiple CAN routes is improved, and the testing efficiency is improved. According to the method and the system, the fault of the whole vehicle or the functional problem caused by the routing error is avoided from the source, the data with the routing problem can be accurately displayed, the test time is greatly shortened, and the speed and the efficiency of the CAN routing test are improved.

The invention relates to the technical field of automobile intelligent network connection testing, in particular to an electric seat testing method, device and equipment. The invention discloses an electric seat test method, which comprises the following steps of: initializing a test process for executing an electric seat test; after a starting instruction of a user is received, a comfortable getting-on test and a comfortable getting-off test are sequentially and repeatedly executed through the test process, and after the comfortable getting-on test and the comfortable getting-off test are executed every time, a test result is determined; and when the number of tests reaches a preset number of tests, completing the test of the electric seat. In the embodiment of the invention, full-automatic testing can be realized only through the infrared sensor and the upper computer, manual testing of a real vehicle is replaced, the operation is simple, long-term manual participation is not needed in the whole testing process, 24-hour uninterrupted testing can be carried out, and meanwhile, the accuracy of a testing result is improved.

The invention provides a memory testing method and device, electronic equipment and a computer readable storage medium, and belongs to the technical field of memory testing. The method comprises the following steps: acquiring the number of application cores, and labeling each application core; obtaining a memory test range of a memory to be tested, distributing a plurality of blocks to be tested for each application core according to the memory test range and the number of the application cores, and numbering the distributed blocks to be tested of each application core; according to the mark number of each application core and the serial number of each to-be-tested block, determining a target test algorithm of each to-be-tested block allocated to each application core from at least two preset test algorithms; and executing a corresponding target test algorithm on each distributed to-be-tested block in parallel through each application core, and obtaining a test result of each to-be-tested block. Therefore, each application core runs different types of preset test algorithms in parallel in the allocated to-be-tested block, so that the diversity test of the memory at the same time is realized, the memory test flexibility and accuracy are improved, and the test time is saved.

The utility model discloses an electrophoretic coating bumping test device for a laboratory, which comprises a bumping test device body, and the top and the bottom of the bumping test device body are both provided with round holes capable of being opened; and the handle lever device is inserted from the round hole which can be formed in the bottom of the bump test device body, penetrates out of the round hole which can be formed in the top of the bump test device body, and is fixed. According to the device, the adjustment design of different variables is integrated in one bump test device, so that two different test objects of workpieces and sample plates with different sizes, a certain number of steel balls with needles with different masses and test time can be realized through simple and convenient adjustment; problems existing in a visual method for testing the scratch resistance of the coating at the present stage are solved by screening proper electrophoresis product models, and finally a product evaluation model is optimized to improve a formula.

The invention provides a semiconductor device with a test element group and a test method of the semiconductor device. The test element group is arranged in a scribing groove in a substrate; n chips adjacent to the test element group share the test element group, and N is greater than or equal to 2; a test circuit is arranged in the test element group, and the test circuit comprises a phase decoder. According to the invention, a plurality of chip sharing test element groups based on phase identification can effectively distinguish sources or positions of a plurality of chips; and the test circuit selects a corresponding chip in the N chips according to the received phase signal, and tests the corresponding chip by using the test element group, and a dynamic identification and selection mechanism is adopted. The probe card is simplified, and the maintenance cost of the probe card is reduced. The number of test pads is reduced, wafer area waste is reduced, the test efficiency is improved, and the test circuit is automatically removed along with the cutting channel after the wafer is tested. The test circuit does not occupy the internal space of the chip, the test time is shortened, and interference and power consumption risks after packaging are reduced.

The utility model relates to the technical field of airplane accessory maintenance, in particular to a testing device of an airplane instruction sensor, which comprises a shell, M detection instruments and a gear selector switch are arranged on the shell; the plurality of test switches are arranged in the shell, and each test switch is electrically connected with a switch to be tested in a sensor through a data line; wherein the plurality of test switches are divided into M groups, each group comprises N test switches, and each group of test switches are connected in parallel to one detection instrument. According to the test device provided by the invention, the states of all test points can be displayed on the test device in sequence only by connecting wires once in the test process and switching the gear change-over switch in the test without replacing and plugging test connecting wires back and forth, so that a large amount of test time is saved, and meanwhile, the device adopts an integrated design, so that the test efficiency is improved. Scattered power supplies, instruments, connecting lines and the like do not need to be externally connected, so that the testing process is more convenient.

The invention discloses an exploder test system, in which a bus rapid connection device specifically comprises a bus main body and male and female butt joint terminals respectively welded at two ends of the bus main body, such a design enables the connection between an exploder and a fixing device to be faster and more convenient, complex line connection and debugging are not needed, and the connection time is greatly reduced; a plurality of channel detection circuits are arranged on the detonation detection plate, whether the electronic control modules of the corresponding digital electronic detonators are normally detonated or not is determined based on turn-on or turn-off of the LED lamps, the state of each module can be rapidly judged through the visual detection mode, complex detection equipment and tedious operation procedures are not needed, and the test efficiency is improved; the technical problems that the existing test system is time-consuming in line connection, limited in test times and environment, and has potential safety hazards are solved.

The invention, which belongs to the technical field of host sleep current automatic testing, provides an automobile intelligent cabin sleep current automatic testing system and testing method, comprising a testing module, an analog power supply module, a domain control host and a current detection module. Before testing, a tester connects the equipment, and starts testing after determining that the equipment is normally connected; the analog power supply module outputs power to the domain control host, and the domain control host works. And after the domain control host works for a period of time, the test module outputs a control instruction to the analog power module to control the analog power module to stop power output. The test module collects the voltage and current of the domain control host in a dormant state in real time through the simulation power supply module and the current detection module, and the test module reads a work log of the domain control host; the test module stops the test when the test reaches the maximum test time; and the test module normalizes the data acquired in the test process. According to the invention, the test efficiency is improved.

The test method, device, equipment and storage medium provided in the application first test each to-be-tested parameter of a preset number of DRAM samples through a system-level test machine and each standard parameter value in a high-temperature environment and a low-temperature environment, to obtain a corresponding first test result, then test each to-be-tested parameter of the DRAM sample with a failed first test result through a test machine and each target parameter value in a normal-temperature environment, to obtain a corresponding second test result. If the second test result is also failed, each to-be-tested parameter of the to-be-tested DRAM is tested through a test machine and each target parameter value in a normal-temperature environment, to realize that the normal-temperature environment replaces the high-temperature environment and the low-temperature environment to perform STL test on the to-be-tested DRAM sample, and test cost and test time are saved.

The utility model discloses a vertical pump cavitation testing device and system, the device comprises an upper component, a partition plate, a to-be-tested impeller assembly with a lower shaft, and a lower component, the upper component comprises a driving assembly and an upper shaft driven by the driving assembly to rotate; the partition plate is arranged between the upper component and the lower component, a liquid inlet area is formed on the lower side of the partition plate, and a liquid outlet area is formed on the upper side of the partition plate; the lower shaft of the impeller assembly to be tested is connected with the upper shaft of the upper component through a coupling; a communication hole is formed in the middle of the partition plate, the lower shaft is arranged in the communication hole in a penetrating mode, and an impeller of the impeller assembly to be tested can drive liquid to enter the liquid outlet area from the liquid inlet area through the communication hole. The cavitation performance measuring device has the advantages of being high in cavitation performance measuring accuracy, simplifying the test process, saving the test time and saving the test cost.

According to the dexterous hand repetitive motion precision testing tool provided by the invention, the zero position limiting assembly is added in the repetitive motion precision testing module, the zero position limiting assembly provides the driving force for the moving block, so that the moving block abuts against the measuring pin of the dial indicator, and the moving block continues to compress the measuring pin under the action of the driving force, so that the measuring pin is accurately measured. When the measuring needle is static, the measuring zero position of the dial indicator measuring needle is located in the middle of the stroke of the dial indicator measuring needle, the measuring zero position of the dial indicator measuring needle is obtained, and therefore the same repeated motion precision testing tool is used for completing repeated motion precision testing of the left hand and the right hand of the dexterous hand. The test time of the repeated motion precision test is shortened; moreover, the repetitive motion precision test of the two hands of the dexterous hand can be completed by designing one test tool for the repetitive motion precision of the dexterous hand, and the design difficulty of the test tool for the repetitive motion precision of the dexterous hand is reduced.

Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.

The application provides a multi-two-dimensional code page decoding test method and device. The method first acquires each two-dimensional code picture in a multi-two-dimensional code page to be tested, and then determines a key parameter field and a key parameter value corresponding to each two-dimensional code picture. For each two-dimensional code picture, it is judged whether the key parameter value corresponding to the key parameter field matches the parameter value corresponding to the preset parameter field, and a judgment result of the two-dimensional code picture is obtained. Finally, a decoding test result of the multi-two-dimensional code page to be tested is generated according to the judgment results of all two-dimensional code pictures, the automatic verification of the decoding content of the two-dimensional code in the multi-two-dimensional code page scene is realized, the test efficiency and accuracy of the correctness of the two-dimensional code parameters are effectively improved, the labor cost is reduced, and the problems of long test time and incompleteness caused by testing the page with multiple two-dimensional codes by using the manual or sampling method are solved.

The invention discloses an automatic test selection method based on a utility function weighted scoring model, and the method comprises the following steps: S1, constructing a comprehensive scoring function which is used for calculating the priority score of a test case; s2, sorting the test cases based on the scores, determining the test cases with the scores higher than a threshold value T as a necessary test group, and determining the test cases with the scores lower than T as a spot check group; and S3, executing the test cases of the necessary test group by 100%, and executing the spot check group by taking a Score (i) normalized value as a probability. According to the method, quantitative evaluation is carried out by introducing three factors of risk, importance and cost, high-value test cases are executed preferentially, and repeated execution of test cases with stable long-term passing rate and low risk is avoided, so that the test time and resource overhead are effectively reduced; besides, factors such as module change frequency, historical defect distribution and function key degree are comprehensively considered, so that the test process is more focused on a potential high-risk path, and exposure of more key defects in an early test stage is facilitated.

The application relates to the technical field of material testing, and particularly relates to a digital twin management method and system based on multi-source data fusion. A test material is placed in a test environment with specified test conditions to collect multi-source monitoring data of the test material in the test environment. The multi-source monitoring data is fed back to a pre-established digital twin, and simulation data corresponding to various test conditions of the digital twin is recorded. The simulation data corresponding to various test conditions is arranged in a test time sequence to obtain test performance information flow of the digital twin. The material properties of the test material are analyzed based on the test performance information flow, and life cycle information flow of the test material in various working environments is constructed according to the analysis result.

The application discloses a chip trimming function test method, device, equipment and medium, and relates to the technical field of chip testing. The method is applied to an automatic test equipment, and comprises the following steps: a general input / output interface is configured for a chip to be tested; a chip test mode is executed according to a test signal in the general input / output interface, and serial data sent by the automatic test equipment is acquired; a data flow direction of the serial data is determined according to a preset data format, and the serial data is written into a trimming register based on the data flow direction. Through the technical scheme, the test method can be simplified, and the test time can be shortened.

The invention provides a multi-power domain chip timing sequence adaptive test system and test method, the system comprises a plurality of timing sequence test devices, each timing sequence test device is connected with a GPU chip, the models of all GPU chips are the same, and each timing sequence test device comprises a timing sequence control module, a timing sequence detection module and a result analysis module. A test scheme of the time sequence test device is formulated according to the test states of the time sequence test device and other simultaneous test time sequence test devices, and a plurality of time sequence test devices are adopted to test the GPU chip at the same time, so that the time sequence test efficiency of the multi-power-domain GPU chip is improved; during testing, the power-on sequence and the rising time delay of the time sequence of the multi-power-domain GPU chip are evaluated, and time sequence parameters of the GPU chip are analyzed more comprehensively; and testing is carried out in a normal working state of the GPU chip, so that the time sequence parameters of the chip in an actual application scene are reflected more accurately.

The embodiment of the application provides a kind of child behavior abnormality evaluation method and system, in the case where the child to be measured is located at least one test scene shown in test room, the behavior test data of the child to be measured collected by the data acquisition equipment arranged in test room is acquired;The behavior test data of the child to be measured is analyzed and processed, and the behavior characteristics of the child to be measured are determined;According to behavior characteristics, the probability that the child to be measured exists behavior abnormality is evaluated.The test scene corresponds to the abnormal behavior type to be evaluated of the child to be measured, and the abnormal behavior type includes at least one performance behavior corresponding to autism spectrum disorder.That is, the behavior test data of the child to be measured in real scene is collected by data acquisition equipment, to record the real action and behavior of the child to be measured comprehensively and accurately.In this way, the possibility of abnormal behavior of the child to be measured can be evaluated by analyzing behavior test data, which shortens the test time and improves the evaluation efficiency of abnormal behavior.

The utility model discloses a cable test system, which comprises a test tool, a routing line instrument and a tested cable which are connected in sequence, and is characterized in that the routing line instrument is used for forming a line configuration scheme according to timing information and the number of cable cores and controlling the on and off of the instrument according to the line configuration scheme; therefore, when the instrument is conducted, the test tool carries out corresponding tests on the tested cable. According to the utility model, the multi-core cable test time can be reduced.

A simulation failure identification and physical acceleration fusion-based MEMS sensor accelerated life test method comprises the following steps: aiming at environmental stress information of an MEMS sensor in a predetermined task process, identifying a failure form and a weak part by using structure simulation, and carrying out simulation evaluation on candidate acceleration stress working conditions constructed around the weak part; according to a preset life, a reliability requirement and a test resource constraint, selecting a combination of a stress level, test time and a sample number from the candidate working conditions to form an accelerated life test design scheme of the MEMS sensor; according to the method, the test period can be shortened on the premise that the test representativeness and accuracy are guaranteed, the test cost is reduced, and the effectiveness and universality of the reliability test design of the MEMS sensor are improved.

The application discloses a kind of multi-station automatic QT test equipment, belong to test equipment technical field, including base frame, assembly line, test piece conveying line, qualified piece conveying line, carrier disc backflow conveying line, defective product conveying line and lifting positioning transfer line assembly, the left end and right end of assembly line are respectively equipped with discharge mechanism and feeding mechanism, by above-mentioned mode, in the present application, feeding mechanism, discharge mechanism, test piece conveying line, qualified piece conveying line, carrier disc backflow conveying line and lifting positioning transfer line assembly constitute the circulation of carrier disc conveying, realize the automatic QT test of test piece, and multiple lifting positioning transfer line assembly and multiple multi-station test mechanism cooperate simultaneously to test piece conveying line on test piece take and place and test, and each multi-station test mechanism simultaneously tests multiple test pieces, reduces test time, significantly improves test efficiency, simultaneously, unqualified piece is placed on defective product conveying line and temporarily stored, waits subsequent processing.

The utility model discloses a test fixture for a hard wire product, which comprises a test base, a support table is arranged on the upper side of the test base, a positioning seat is arranged at the top of the support table through a connecting seat, a test chuck is inserted in the positioning seat, a plurality of test insertion seats are arranged in the test chuck, and a wire conduit is arranged at the lower end of each test insertion seat. The upper end of the supporting table is provided with a test chuck, a test insertion seat, a conduit tube and a bent positioning tube, the lower side of the conduit tube is provided with a bent positioning tube, the middle part in the supporting table is provided with a test groove, and one end of the bent positioning tube is electrically connected with a test wiring end of the test groove through a lead. The lead-out wire of the product is inserted into the bent positioning tube, the lead-out wire is quickly connected with the test wiring end, the positioning stability is high, disassembly and assembly are convenient, the product test time is greatly shortened, the test difficulty is greatly reduced, and the test reliability is greatly improved.