342 results about "Tests times" patented technology

The invention provides a chip testing method and system, and relates to the technical field of chip testing. According to the invention, in response to a material receiving control instruction, the adsorption devices of the plurality of test assembly lines are controlled to alternately move to the feeding machine and adsorb the tested chips on the feeding machine, and then the adsorption devices are controlled to sequentially carry the tested chips to each carrying device; each carrying device is used for carrying the tested chip to the corresponding testing mechanism for functional testing, and finally, after testing of the tested chip is completed, the adsorption device is controlled to carry the tested chip to the discharging machine for discharging. According to the technical scheme, the adsorption devices of the multiple test assembly lines are controlled to alternately adsorb the tested chips and alternately discharge the tested chips, so that the waiting time of the feeding machine and the discharging machine can be shortened, feeding and discharging can be carried out without interruption, the test efficiency of the test system is improved, and the test time is saved.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The invention provides an equipment reliability test profile generation method based on a quantitative acceleration test, and relates to the technical field of acceleration tests, and the method comprises the steps: obtaining a reliability index for target equipment, and carrying out the statistics of a test scheme; according to the reliability index and the statistical test scheme, determining the total conventional test time and the reference cycle index for the target equipment; determining an acceleration stress value corresponding to the target stress according to the working limit of the target equipment for the target stress; calculating an acceleration factor of the target stress according to a reference stress value and an acceleration stress value of the target equipment for the target stress; and according to the conventional test profile, the reference stress value, the reference cycle index, the acceleration stress value, the acceleration factor and the total conventional test time of the target equipment, a reliability acceleration test profile of the target equipment is generated, and the reliability acceleration test profile is used for performing a reliability acceleration test on the target equipment for the reliability index. Therefore, the universality of the test is improved, and the test time is shortened.

The present invention discloses an integrated circuit chip testing system based on an AI algorithm, which relates to the field of integrated circuit chip testing technology and includes a chip testing platform. The chip testing platform is communicatively connected to the following modules, including: a data acquisition module for collecting historical test data from existing integrated circuit chip testing equipment, preprocessing the data, and integrating the data to obtain a chip test data set; a model training and optimization module for analyzing the chip test data set, learning the relationship between chip performance and test vectors, and training a test vector AI optimization model. The present invention automatically generates optimized test vectors by analyzing historical test data, avoiding the redundant item-by-item test process in traditional testing, accurately locating key test nodes through the test vector AI optimization model, reducing unnecessary test steps, thereby significantly shortening test time and improving test efficiency.

The invention discloses an aircraft parallel collaborative test method, device and equipment and a storage medium, and the method comprises the steps: decomposing a total test process of a single aircraft, and obtaining a plurality of test items of the single aircraft; sorting the plurality of test items on the basis of the association and dependency relationship among the test items, and sorting the test items of the plurality of aircrafts in sequence on the basis of a sorting result to obtain a double-code network diagram of the plurality of aircrafts; based on the double-code network diagram, identifying a test item link with longest time consumption when a plurality of aircrafts are tested at the same time, so as to generate a critical path; and based on the established test process optimization model, optimizing all test items on the critical path by taking test time and test resources as optimization targets, and outputting an optimal parallel test scheme of the plurality of aircrafts. The aircraft test launching efficiency and the resource utilization rate can be effectively improved, the preparation time is shortened, and it is ensured that the test process is completed on time with high quality.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The embodiment of the invention discloses a multi-channel test method, electronic equipment and a test system thereof, and the method comprises the steps: receiving first identification information obtained by scanning of scanning equipment, and selecting a corresponding test channel according to the first identification information; the test channel is provided with a to-be-tested circuit board in advance; receiving second identification information obtained by scanning the to-be-tested circuit board by the scanning equipment; sending a test instruction to the test equipment on the corresponding test channel to enable the test equipment to test the to-be-tested circuit board according to a pre-configured test item to generate test data; and obtaining test data, and storing the test data according to the second identification information. By means of the mode, multi-channel parallel test preparation can be achieved, the test efficiency is improved, the overall test time is shortened, and therefore the test cost and human resource investment are reduced; and cloud storage and tracing of test data can be realized.

The utility model discloses a hydraulic drive type automatic dynamic penetration testing machine which comprises a base, a console and a lifting mechanism are arranged on the base, an automatic hammering device is arranged on the lifting mechanism, and the lifting mechanism and the automatic hammering device are both connected with the console through hydraulic pipelines. According to the utility model, the operating platform is adopted to regulate and control the working state of the lifting mechanism through pressure oil, so that the automatic hammering device can automatically lift and drop a hammer, the purpose of automatic hammering is achieved, the tedious process of manual operation is avoided, each hammering penetration depth can be recorded through the operating platform, the test time is effectively saved, the test efficiency is improved, and the test cost is reduced. And moreover, recording errors caused by manual counting of testers are prevented, the authenticity and accuracy of the test are ensured, the test efficiency is improved, and the device has the characteristics of convenience in installation, convenience in operation and the like.

The invention relates to a parallel test task scheduling method for a multi-target equipment distributed test system, and belongs to the technical field of scheduling methods. The invention provides a parallel test task scheduling method for a multi-target equipment distributed test system and aims to solve the problems that current equipment models are continuously increased, the number and complexity of equipment test tasks are obviously increased, a traditional test method is long in test time and low in resource utilization rate, and equipment test requirements at the current stage cannot be met. The method can obviously shorten the test time and improve the resource utilization rate, and comprises the following steps: step 1, describing an equipment parallel test task scheduling model by adopting a mathematical method; step 2, determining a constraint relationship of the test task on test time sequence and resources and a constraint condition satisfied between the test task and the test resources; 3, determining a fitness function corresponding to the test time and the resource utilization balance degree, and designing an overall fitness function; and step 4, solving the fitness function.

The invention provides a double-station radio frequency chip high-low temperature high-speed test sorting machine which comprises a test assembly, and the test assembly comprises a shell, a workbench, a preprocessor, a first air inlet pipe, a first exhaust pipe, a placing device and a detection table; the inner side wall of the shell is fixedly connected with a workbench, two preprocessors are symmetrically installed on the top of the workbench, the outer side walls of the preprocessors communicate with an air inlet pipe and an exhaust pipe, and the top of the workbench is symmetrically and fixedly connected with two detection tables. The chip is preprocessed through the preprocessor, it is ensured that the chip reaches the required test temperature before entering the detection table, and therefore the overall test time is shortened. The test cover slidably connected to the test bench facilitates rapid replacement of the test chip, and further improves the test speed. By adding the double testing stations, testing can be carried out alternately, two groups of chips can be tested at the same time, the waiting time is shortened, and the testing efficiency is improved.

The invention relates to a TSN network minimization intrusive test scheduling method for guaranteeing production safety priority, which comprises the following steps: step 1, reservation of time-space isolated test resources: distributing a special test time slot with the lowest priority for test flow in a scheduling period of a centralized network controller; and step 2, a dynamic detection strategy of service awareness: monitoring key performance indexes of the key production service queue in real time, and when all the key performance indexes are lower than a preset threshold value, injecting test flow in a test time slot. And step 3, adaptive network optimization of closed loop feedback. According to the invention, on the premise of not influencing the normal operation of the key production service under the coal mine, the accurate and real-time monitoring of the TSN network state can be realized, the non-inductive test effect of the service is finally achieved, and the self-adaptive optimization capability is realized.

The invention provides an in-situ monitoring immersed cooling liquid and server compatibility testing device and testing method. The device comprises an inner-layer shell, a server host, a cooling liquid circulation module, a ventilation module, a temperature control module, an electrical property sensor module, a data acquisition module and a control module. The temperature control module monitors and adjusts the temperature of the cooling liquid in real time, the test time is remarkably shortened, and the test efficiency is improved; the cooling liquid circulation, ventilation and temperature control module highly reduces the real service environment of the cooling liquid and the server host; the server host is used as a tested object and a control center and is responsible for automation of data acquisition, processing, display, recording and control, so that the automation degree is higher; a temperature measuring element and an electrical performance sensor in the temperature control module monitor the temperature and the electrical performance of the cooling liquid in real time and feed back data in time, so that problems can be found quickly and timely, meanwhile, the appearance state of the server host is observed, and the compatibility of the cooling liquid and the server is evaluated comprehensively.

The invention relates to the technical field of chip function testing, and particularly discloses a multi-site testing method for TOF sensor chip function testing, which comprises the following steps: completing hardware self-inspection and software loading; the host receives a'ready 'signal fed back by the sorting machine / probe station through GPIB communication, and confirms that each slave and the corresponding peripheral are in a'to-be-tested' state through TCP communication or Pipe interaction; the host issues an independent test instruction to each slave; after each slave receives the instruction, the corresponding test resource board card is controlled to provide a test condition for the chip to be tested, and the chip output data is collected at the same time; after completing the single-station test, each slave uploads a test result to the host; the host captures the test data from the corresponding network disk and counts the yield; and the host sends the final result of the multi-station test to the sorting machine / probe station through the communication driver and automatically grabs the next batch of chips to be tested. According to the method, the overall test time is greatly shortened through the multi-site parallel test.

The invention discloses a test case execution method, electronic equipment, a storage medium and a program product, and relates to the technical field of testing, the explicit dependency relationship among test cases is identified according to a test case set, and the implicit dependency relationship among the test cases is identified according to historical execution data; according to the identification result of the explicit dependency relationship and the implicit dependency relationship, a dependency graph of the test case set is constructed, the dependency graph is constructed in a mode of combining the static test case set and the dynamic historical execution data, so that the constructed dependency graph is more accurate, and then the dependency type of the test case is determined according to the dependency graph. The execution sequence of the test cases in the test case set is determined according to the dependency types, so that different characteristics of the test cases of different dependency types are considered, the test efficiency is improved, tests are executed according to the execution sequence, invalid tests are prevented from being executed, the test time is shortened, and the test cost is reduced; the technical problems of low test efficiency and high test cost in related technologies are solved.

The invention discloses a high-temperature melt viscosity testing device and method, and the testing device comprises a testing box; a visual assembly is arranged on one side of the test box; an adjusting mechanism, wherein the test box and the visual assembly are arranged above the adjusting mechanism; collecting the change state of the material in the test box through the visual component, and calculating the viscosity of the material; image data of materials in the testing box can be monitored in real time through the visual assembly, the viscosity of the materials is calculated according to the change of size data, the testing box can control the temperature and atmosphere, the high-temperature melt viscosity in different testing environments can be conveniently adjusted, testing is easy and convenient, the sample preparation size is small, and the testing time is short.

The invention relates to a test time training method based on invariant graph learning, and the method comprises the following steps: 1, a joint training stage, a joint training encoder fg, a main task classification head pi m and self-supervision task classification heads pi s1 and pi s2 are trained through a graph classification task and an auxiliary self-supervision task by using marked training set data, and the joint training stage is divided into two parts including invariant graph recognition and multi-level graph comparison learning; step 2, in a test time training stage, realizing self-adaption of the model on test data by minimizing the difference of feature distribution of a training domain and a test domain; and step 3, a test stage: in a model test stage, carrying out specific processes and strategies of model evaluation and fine adjustment by using a test sample. According to the scheme, through a test time training method, the model is finely adjusted by using label-free test data distribution, and the generalization performance of the model in a distribution offset scene is improved.

The invention provides an enhancement method for a question answering system during testing based on reinforcement learning, and belongs to the technical field of natural language processing. The method aims at solving the technical problems that an existing large language model (LLM) faces knowledge blind areas, reasoning chain breakage and context length limitation in a question and answer (QA) task, an existing fine adjustment method is high in calculation cost and damaged in generalization ability, and a prompt strategy seriously depends on a limited context window and lacks long-term memory. The method comprises the following steps: firstly, collecting reflection experience through multiple attempts and a failure reflection mechanism, and constructing an experience library; thirdly, performing text embedding, clustering and semantic abstracting on experiences in the experience library, and constructing an external memory library; secondly, a memory selection process is formalized into a Markov decision process (MDP), reinforcement learning (such as a PPO algorithm) is used for training a strategy agent, and the agent is optimized with a current task as a state, with memory item selection as an action and with LLM answer correctness as a reward; finally, in a test time (inference) phase, the agent dynamically selects the most helpful memory entry according to the new task and integrates it into the hint of the LLM to generate a final answer. According to the method, under the condition that LLM internal parameters do not need to be updated, the question and answer accuracy is dynamically improved, the calculation overhead is reduced, and the limitation of a context window is effectively overcome.

The invention relates to a computer-implemented method for synchronizing a simulation with a test, wherein the simulation provides output data in response to input data, comprising the following method steps: S1) Transferring an input date from the test to the simulation so that the simulation determines an output date, simultaneously starting a test time and a simulation time so that an elapsed test time and an elapsed simulation time can be retrieved, and transferring the determined output date from the simulation to the test, S2) Retrieving the test time and retrieving the simulation time and comparing the simulation time with the test time, S3a) if the comparison has shown that the simulation time corresponds to or exceeds the test time: transferring a further input date from the predetermined set of input data from the test to the simulation, so that a further output date is determined by the simulation based on the further input date, or terminating the process if all input data have already been transferred to the simulation, and S3b) if the comparison has shown that the simulation time is less than the test time: pausing the test for a pause time during which the expiration of the test time is stopped, and repeating step S2 and subsequently step S3a or S3b after the pause time. In this way, a method is provided that enables precise synchronization.

This invention discloses a shoe wear simulation test circuit and method. The shoe wear simulation test circuit includes at least an EBS controller, and the shoe wear simulation test method includes: acquiring the current test voltage, providing the current test voltage to the EBS controller, and receiving the current feedback signal output by the EBS controller; determining the current theoretical remaining wear of the shoe based on the current test voltage; determining the current tested remaining wear of the shoe based on the current feedback signal; and determining the current test result based on the current theoretical remaining wear and the current tested remaining wear. The technical solution of this invention can realize the simulation test of shoe wear detection function in a laboratory environment, with short test time and high accuracy, thus improving the reliability and safety of the braking system.

The present invention belongs to the technical field of integrated circuit testability design, and discloses a 3D IC MBIST test method based on an intelligent algorithm. It performs isomorphic grouping by parsing the spatial coordinates, hierarchical attribution, and multi-dimensional attributes of memories; establishes a three-dimensional layout relationship based on an improved interlayer distance model; uses a hierarchical clustering algorithm to merge memory clusters according to spatial proximity, and constructs a grouping architecture with a minimized number of controllers; combines a multi-objective simulated annealing algorithm to establish a dynamic test scheduling model, and optimizes the test time under power consumption constraints through a temperature attenuation mechanism. The method of the present invention performs three-dimensional collaborative optimization of spatial layout, timing constraints, and power consumption budget, solves the contradiction between area overhead and test efficiency faced by traditional memory built-in self-test schemes in 3D ICs, effectively copes with the stacked layer test challenges under limited test temperature conditions, and significantly improves the test economy and reliability of heterogeneous integrated chips.

The application provides a press-pack IGBT sub-module test adapter and a test device. The press-pack IGBT sub-module test adapter comprises a lower clamp. The lower clamp comprises: a conductive base plate, the conductive base plate having an array of positioning holes, the array of positioning holes comprising a plurality of separate positioning holes; a positioning assembly, the positioning assembly comprising a conductive adapter, the conductive adapter being adapted to be placed on the array of positioning holes, the conductive adapter being provided with a first recess, the first recess being adapted to place a to-be-tested sub-module; and a first fastener, the first fastener being adapted to penetrate the conductive adapter on the side of the first recess and extend in at least part of the positioning holes. When the structure of the to-be-tested sub-module changes, the structure of the whole adapter does not need to be redesigned, the universality of the adapter is improved, and thus the test cost is reduced and the test time is shortened.

The invention provides a battery testing method, device and equipment and a testing system. The performance loss condition of a battery can be obtained through short-term testing. The test method comprises the following steps: acquiring cycle parameters of a battery, wherein the cycle parameters comprise performance parameters of the battery corresponding to execution of a predetermined number of cycle operations; and determining the performance loss of the battery in a single cycle operation according to the cycle parameters. The performance loss rate of the battery is obtained by utilizing the performance parameter change caused by executing the cycle operation in a short time, so that the test efficiency can be improved, and the test time and test resources are saved.

The application belongs to the technical field of automatic test program, and particularly relates to a LabVIEW test method of a multi-channel programmable output clock buffer. The method comprises the following steps: initializing the clock buffer after power-on; resetting the FSWP spectrum analyzer and clearing the previous interface settings; switching the radio frequency switch to channel 1 and opening the channel 1 output; setting the signal source input frequency; setting the signal source input amplitude; starting the signal source input, and outputting the set frequency and amplitude to the input end of the clock buffer; starting the register configuration module, and transmitting the 174 24-bit register values to the SPI in sequence through the serial port, and then transmitting the SPI to the clock buffer; reading the data on the FSWP spectrum analyzer; and the method automatically measures the key indicators of the 14-channel clock buffer, saves the data and judges the advantages and disadvantages. The method reduces the burden of the test personnel, reduces the test time cost, and avoids causing data errors.

The invention discloses a CAN routing test function implementation method, device and equipment and a storage medium, and the method comprises the steps: obtaining original CAN data through collection, carrying out the preprocessing of the original CAN data, and obtaining the preprocessed target CAN data; extracting key information of a routing message from the target CAN data, and obtaining difference data according to the key information; the difference data is displayed through the display module, multiple CAN channels can be tested, the testing method is friendly, the automation degree is high, compatibility is high, the testing efficiency can be greatly improved, automatic testing is achieved, the accuracy of testing routes under the condition of multiple CAN routes is improved, and the testing efficiency is improved. According to the method and the system, the fault of the whole vehicle or the functional problem caused by the routing error is avoided from the source, the data with the routing problem can be accurately displayed, the test time is greatly shortened, and the speed and the efficiency of the CAN routing test are improved.

The present invention discloses a method for determining the flotation design time based on laboratory flotation closed-circuit tests, which is determined according to the data obtained in the flotation closed-circuit tests. The data includes the minimum number of test groups required to reach the equilibrium state in the test, the total weight of middlings in a single-group test after reaching the equilibrium state, and the data of the additional water volume in a single-group test after reaching the equilibrium state. The present invention can accurately calculate the flotation design time, so as to achieve a high degree of fitting between the flotation design time and the laboratory closed-circuit flotation test time, make a reasonable evaluation of the flotation time of the existing production process, and can also provide accurate data for the subsequent process design and equipment selection. It is applicable to the process design and flow diagnosis of most metal ore beneficiation processes, and has the characteristics of simple calculation and strong practicability.

The utility model discloses a nuclear power station priority module interface test system. The risk of misoperation of a safety-level actuator is reduced, and the test automation level is improved. The interface test system comprises a security level control and display device, an RPS bypass device, three security level controllers and n priority modules, wherein n is greater than or equal to 1; the three security level controllers are respectively an SETA controller, an SETB controller and a third controller; the X controller comprises a bypass state judgment unit, a test instruction triggering unit, a test time control unit, n real instruction locking units and n DO driving logic units; x is equal to SETA and SETB; the RPS bypass device is connected with the X controller; the security level control and display device is connected with the three security level controllers; and the third controller comprises n SETA test feedback processing units and n SETB test feedback processing units.

The invention relates to the technical field of automobile intelligent network connection testing, in particular to an electric seat testing method, device and equipment. The invention discloses an electric seat test method, which comprises the following steps of: initializing a test process for executing an electric seat test; after a starting instruction of a user is received, a comfortable getting-on test and a comfortable getting-off test are sequentially and repeatedly executed through the test process, and after the comfortable getting-on test and the comfortable getting-off test are executed every time, a test result is determined; and when the number of tests reaches a preset number of tests, completing the test of the electric seat. In the embodiment of the invention, full-automatic testing can be realized only through the infrared sensor and the upper computer, manual testing of a real vehicle is replaced, the operation is simple, long-term manual participation is not needed in the whole testing process, 24-hour uninterrupted testing can be carried out, and meanwhile, the accuracy of a testing result is improved.

The invention provides a memory testing method and device, electronic equipment and a computer readable storage medium, and belongs to the technical field of memory testing. The method comprises the following steps: acquiring the number of application cores, and labeling each application core; obtaining a memory test range of a memory to be tested, distributing a plurality of blocks to be tested for each application core according to the memory test range and the number of the application cores, and numbering the distributed blocks to be tested of each application core; according to the mark number of each application core and the serial number of each to-be-tested block, determining a target test algorithm of each to-be-tested block allocated to each application core from at least two preset test algorithms; and executing a corresponding target test algorithm on each distributed to-be-tested block in parallel through each application core, and obtaining a test result of each to-be-tested block. Therefore, each application core runs different types of preset test algorithms in parallel in the allocated to-be-tested block, so that the diversity test of the memory at the same time is realized, the memory test flexibility and accuracy are improved, and the test time is saved.

The utility model relates to the field of equipment testing, in particular to a testing system for high and low temperature reliability aging testing. According to the utility model, an incubator, a vibration table, PC control and system test in the existing detection scheme are integrated into a set of system, temperature control is realized through a Python frame, vibration test, high and low temperature test, system function test and long-time reliability test corresponding to equipment are carried out, and real-time monitoring is carried out through a camera, so that the detection efficiency is improved. According to the utility model, the performance transparency and visualization of the equipment in the whole high and low temperature process are ensured, the real working environment of the locomotive equipment can be simulated by adjusting the parameters of high and low temperature, vibration and the like, the authenticity and credibility of test data are enhanced, and the test time is greatly shortened.