1439 results about "Tests times" patented technology

A shift scan chain includes logic circuit blocks 11-18 and scan registers 21-28 connected at stages succeeding them. The shift chain is divided into divisional chains including the scan registers 21-24 and the scan registers 25-28. In the test operation mode of a semiconductor integrated circuit, test input data TI are supplied in synchronism with a multiplied clock signal CKD at a frequency twice of that of a clock signal CK. The test input data TI are converted by a serial/parallel conversion circuit 40 into parallel data S41 and S42, which are respectively supplied to the head scan registers 21 and 25 of the corresponding divisional chains. The length of each divisional chains becomes ½, and a test time period can be shortened.

A diagnostic testing kit for collection of fluid samples comprising a reservoir cup insertable into a container vessel. Fluid placed in the cup is communicated to reactive test strips located in a separation cavity between the cup and the container vessel when assembled. The test strips have a reactive agent impregnated in them that reacts to specific substances in the fluid and provide a visual result through the sidewall of the container vessel to the user. An optional alarm is provided to show minimum and maximum test times.

A system and method for continuous online safety and reliability monitoring is disclosed. The method includes the steps of obtaining operating information about at least one of a plurality of instrumented function components, which are part of an instrumented function, and determining a probability of failure on demand for the instrumented function based on the operating information. In variations, operating information includes status information, which may be received from and/or provided to an asset management application. In some variations, instantaneous probability of failure on demand, online mean time to failure (MTTF), and online safety integrity level (SIL) are also calculated for an instrumented function. In yet further variations, the system allows a user to predict probability of failure on demand values into the future based on hypothetical and/or future planned test times.

A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

A new digital architecture for metallic pipe and cable locators, providing accurate estimation of the fundamental locate parameters, electromagnetic signal strength and signal direction, and utilizing a nested Digital Phase-Locked Loop (DPLL) structure is disclosed. The obstacles to signal direction measurement in low SINR environments using the signal select method are overcome and a more precise phase comparison between the carrier and the FM modulation signals is obtained. The architecture further significantly reduces analog front-end hardware requirements, offers wider resistance to component tolerances, lower calibration and test time, and provides flexible frequency selectivity. Locators according to the present invention provide accurate estimation of the fundamental physical parameters of line location (electromagnetic signal strength and signal direction) in extremely noisy environments, using Digital Signal Processing (DSP) methods.

The invention relates to a method for predicting the cycle life of a battery pack for an electric car. The method comprises the following steps: step I, carrying out standard capacity test on the battery pack at normal temperature, and recording a real standard capacity of the battery pack; step II, carrying out dynamic stress working condition circulating test on the battery pack, returning to the step I after multiple times of working condition circulating test is ended, recording the test times of the standard capacity, ending the circulating test at the temperature if the real capacity of the standard capacity test for continuous 4 to 6 times is less than 80 percent of the rated capacity, wherein the test times of the standard capacity indicate the cycle life of the battery pack; step III, repeating the step I and the step II, and testing the cycle life of the battery pack under multiple temperature points. According to the method, the battery pack cycle life data at the grouped time is collected, a fitted equation is obtained by virtue of data processing, and the cycle life of a lithium ion battery at present can be predicted.

A testing method and circuit used to test high-speed communication devices on Automatic Test Equipment—ATE. The method and circuit provide a solution to testing very high speed (2.5 Gbps and above) integrated circuits. The circuit fans out the data streams from the output of the Device Under Test (DUT) to multiple tester channels which under-sample the streams. The testing method and circuit also allow for the injection of jitter into to the DUT at the output of the DUT. The skipping of data bits inherent in multi-pass testing is avoided by duplicating the tester resources to achieve effective real-time capture (saving test time and improving Bit Error Rate). Moreover the circuit synchronizes different DUTs with the timing of ATE hardware independent of DUT output data. Also, a calibration method is used compensate for differing trace lengths and propagation delay characteristics of test circuit components.

The present invention describes a system for recognizing objects from color images by detecting features of interest, classifying them according to previous objects' features that the system has been trained on, and finally drawing a boundary around them to separate each object from others in the image. Furthermore, local feature detection algorithms are applied to color images, outliers are removed, and resulting feature descriptors are clustered to achieve effective object recognition. Additionally, the present invention describes a system for extracting foreground objects and the correct rejection of the background from an image of a scene. Importantly, the present invention allows for changes to the camera viewpoint or lighting between training and test time. The system uses a supervised-learning algorithm and produces blobs of foreground objects that a recognition algorithm can then use for object detection/recognition.

In recent years, much effort has been placed on improving the performance of timing and jitter measurement devices using Delay Locked Loop (DLL) and Vernier Delay Line (VDL) techniques. However, these approaches require highly matched elements in order to reduce differential non-linearity timing errors. In an attempt to reduce the requirement on element matching, a component-invariant VDL technique is disclosed that enables the measurement device to be synthesized from an RTL description. The present invention is based on a single-stage VDL structure, which is used to mimic the behavior of a complete VDL. Furthermore, as test time is an important consideration during a production test, a method and system is provided that reduces test time at the expense of additional hardware.

An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture and storing corresponding diagnosis data which include an indication of the failure-causing test data and the corresponding test analysis data. Embodiments are provided which enable that the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test, together with respective diagnosis data.

The invention discloses a compressive guarantee system for equipment based on an IETM. The compressive guarantee system comprises a business system and a platform support system, wherein the business system comprises an IETM system, a training learning system, an automatic test and diagnosis system, a maintenance support informatization system and a knowledge base system, wherein the platform support system comprises a cloud platform storage system and a compressive management system. The compressive guarantee system disclosed by the invention is combined in image-text, linked in audio and video, visual and intuitional, and friendly to interface, and is capable of carrying out three-dimensional demonstration, operation and decomposition, automatic navigation, depth search, phenomenon and fault association, automatic test and smart fault analysis; the compressive guarantee efficiency is improved; the operating error rate is reduced; the use and maintenance complexity of the system is lowered; the fault treatment time is shortened; the test time is shortened; the compressive guarantee system is a scientific and reasonable training system; the training learning cycle is shortened; a knowledge base system is accumulated and shared; and the dependence on personal experience is reduced.

A microcomputer includes a memory such as a flash memory; a logical circuit such as a CPU; a test ROM storing a test program for testing at least the logical circuit; and recording means capable of storing, as a flag, the result of testing at least one of the memory and logical circuit. The memory and the logical circuit are tested simultaneously to shorten test time. The test-result flag is checked upon being stored. When the flag indicates failure of the logical circuit, testing of the memory is aborted, and vice versa.

The invention relates to the field of gas field development research, in particular to a method for predicting dynamic open-flow capacity of fractured horizontal wells for tight sandstone gas reservoirs. The method includes coupling gas reservoirs, fracture and wellbores to obtain gas and liquid two-phase flow productivity equations for optional fracture locations of the fractured horizontal wells; building corresponding fractured horizontal well numerical models on the basis of reservoir stratum parameters and fracture parameters to obtain relation curves and fitting relational expressions of non-dimensional gas release boundaries and gas test time; computing gas release boundaries of the fractured horizontal wells at production phases by the aid of dynamic reserves inverse processes; solving the gas and liquid two-phase flow productivity equations on the basis of phase permeability curves obtained by rock core tests so as to obtain the dynamic open-flow capacity of the fractured horizontal wells at the different production phases. The method has the advantages that influence of difference of physical parameters of reservoir strata, change of the fracture parameters, difference of gas well open-flow test time, external fracturing fluid and movable water of formations on open-flow capacity is taken into consideration, accordingly, the open-flow capacity of the fractured horizontal wells at the different production phases can be predicted by the aid of the method, and the prediction practicality and reliability can be improved.

The invention relates to a rack test method for accelerating service life and estimating the reliability of a vehicle motor driving system. By considering actual operation environments and work conditions of a vehicle motor system, a service life factor and a corresponding average service life can be calculated through specifically analyzing different failure mechanisms and influence factors of all key parts, so as to establish a service accelerating curve of al the key parts; and invalid data of all the key parts under a normal stress condition are obtained through extrapolating the curve. And then, a service life predicated value of the vehicle motor driving system is obtained according to the data, and determined replacing or maintaining time of the vehicle motor driving system is displayed to a user. By utilizing the rack test method to carry out rack service life examining test, the test time can be effectively reduced, the cost is reduced and the researching period is shortened; and the rack test method disclosed by the invention can help workers of electric vehicle manufacturers or vehicle 4S stores to conveniently know about the service life of the vehicle and the replacing or maintaining time of the vehicle.

The invention relates to a self-weighing method for a drum-type washing machine. Firstly, controlling a motor to reach a first preset speed and to rotate at the first preset speed constantly, and measuring the torque of the motor rotating constantly at the first preset speed; secondly, controlling the motor to accelerate from the first preset speed to a second preset speed, and measuring the accelerating torque of the motor accelerating from the first preset speed to the second preset speed; thirdly, controlling the motor to rotate constantly at the second preset speed, and measuring the torque of the motor rotating constantly at the second preset speed; and finally, working out a corresponding load torque by subtracting an average value of the torque of the motor rotating constantly at the first preset speed and the torque of the motor rotating constantly at the second preset speed from the accelerating torque of the motor accelerating from the first preset speed to the second preset speed according to the test results, and after a correction step, comparing the obtained load torque with a curve, pre-stored in a computer controller of the washing machine, of the corresponding relation of a load torque and a load weight to obtain a most similar weight data. The method has the advantages of high test accuracy and short test time.

A mixed-signal core disclosed herein is designed for efficient concurrent testing analog, mixed-signal, and digital components. One tester may test all components and, thereby, reduce test time without losing full test coverage. An analog module includes all the analog and mixed-signal components of the mixed-signal core, while a first digital module includes digital components required for functional/parametric verification of the mixed-signal components within the analog module. A first virtual boundary connects the analog and the first digital modules to gate the signal transfer during testing. A second digital module includes the remaining digital components of the mixed-signal core, whereby a second virtual boundary separates it from the first digital module. This type of partitioning enables the mixed-signal core to have three modes of operation, wherein the first mode of operation provides digital interface characterization testing of the first and second digital module and analog characterization/trimming testing of the analog module. In the second mode of operation, concurrent testing of the analog module and the first and second digital module is conducted; wherein analog characterization/trimming testing is performed on the analog module and digital interface characterization testing is performed on the first digital module, while SCAN/BIST testing is performed on the second digital module. In the third mode of operation, non-concurrent testing of the analog module, the first digital module, and the second digital module is enabled; wherein SCAN/BIST testing of the first digital module and the second digital module is enabled, while the analog module is powered down.

Power balancing techniques are provided for improving power efficiency of pipelined processors. A design-level implementation can be incorporated during synthesis of pipeline clocks in which a register transfer level (RTL) code, operating frequency, and available voltage domains are used to perform cycle time stealing with, and optimize for, power efficiency. A test-level implementation can be incorporated during testing of a chip in which delay and power measurements are used to perform calculations based on cycle time stealing and optimization of power efficiency. The calculations are then used to perform voltage scaling and/or adjust tunable delay buffers. Process variations may also be corrected during test time. A run-time approach can be incorporated for dynamic power balancing in which the operating system keeps track of one or more performance indicators such as a count of floating point instructions and uses a look-up table to provide the appropriate delays.

A method for reducing the switching activity during both scan-in and scan-out operations of an integrated circuit with reduced detrimental effect on test pattern effectiveness and test time is described. The method makes use of a sample set of patterns to determine the probabilities of same and opposite relationships between stimulus and result values, and uses these probabilities to determine memory element pair compatibilities. Scan chains are ordered preferentially by connecting adjacently compatible memory elements, and inversions are inserted between selected memory element pairs based on those probabilities. Unspecified stimulus bits are filled in to reduce the switching activity based on the scan chain ordering and inversions.