633 results about "Tests times" patented technology

The invention discloses a solid state disk testing method and system, a storage medium and a program product, and relates to the field of computer storage testing, and the method comprises the following steps: dividing a storage space of a solid state disk to be tested into a plurality of physical areas; determining the number of read-write tests of the to-be-tested solid state disk within a preset duration at a preset temperature; performing read-write test operation on the plurality of physical areas in sequence within a preset duration to obtain read-write error rates respectively corresponding to the plurality of physical areas, the number of read-write times of the read-write test operation being the number of read-write test times; if the read-write error rates corresponding to the physical areas exceeding the preset number are higher than a preset error rate threshold value, determining that the to-be-tested solid state disk is unqualified; and if the read-write error rates corresponding to the physical areas lower than the preset number are lower than a preset error rate threshold, determining that the to-be-tested solid state disk is qualified. By implementing the method, the specific problem area in the solid state disk can be positioned and diagnosed more accurately, so that the quality evaluation standard and the maintenance efficiency of the whole solid state disk are improved.

The invention relates to the technical field of automation equipment, and discloses a three-temperature test sorting machine, which is characterized in that a heat preservation cover is arranged on a workbench, and a test space is formed by the heat preservation cover and the workbench, so that the consistency of temperature in the test space can be ensured, a chip is uniformly heated in the test space, and automation of three-temperature test of the chip is realized. The temperature of the chip is adjusted in advance by additionally arranging the pre-heating device, so that the whole chip is heated more uniformly, and meanwhile, the waiting time is fully utilized to adjust the temperature in advance, so that the test time is saved, the accuracy of a chip test result and the stability of a test yield can be ensured, and the test efficiency is improved. Moreover, the test efficiency is improved, and large-scale popularization and application are facilitated.

The invention provides a chip testing method and system, and relates to the technical field of chip testing. According to the invention, in response to a material receiving control instruction, the adsorption devices of the plurality of test assembly lines are controlled to alternately move to the feeding machine and adsorb the tested chips on the feeding machine, and then the adsorption devices are controlled to sequentially carry the tested chips to each carrying device; each carrying device is used for carrying the tested chip to the corresponding testing mechanism for functional testing, and finally, after testing of the tested chip is completed, the adsorption device is controlled to carry the tested chip to the discharging machine for discharging. According to the technical scheme, the adsorption devices of the multiple test assembly lines are controlled to alternately adsorb the tested chips and alternately discharge the tested chips, so that the waiting time of the feeding machine and the discharging machine can be shortened, feeding and discharging can be carried out without interruption, the test efficiency of the test system is improved, and the test time is saved.

The invention discloses UFS equipment and a self-testing method thereof, electronic equipment and a storage medium, and relates to the technical field of UFS equipment testing. The method comprises the following steps: when a T-RX module successfully analyzes a first speed switching request frame constructed by a T-TX module based on a first target speed mode, switching a working mode of a physical layer from a current speed mode to the first target speed mode; initial feature data constructed by the T-TX module is transmitted to a data path based on a first target speed mode and then is received by the T-RX module to obtain return feature data; performing verification processing on the initial feature data and the return feature data to obtain a verification result, determining a path test condition in a first target speed mode, and completing one-time data path test; and when the verification result is correct, the next candidate speed mode is switched for testing until all the candidate speed modes are traversed, and the self-testing is ended. Self-testing can be achieved, the testing time is shortened, the testing efficiency is improved, and the testing cost is reduced.

The invention provides a vehicle body coating filamentous corrosion testing method which comprises the following steps: destroying a coating on the surface of a test piece, exposing a metal matrix, and cleaning chips on the surface of the test piece; introducing an electrolyte solution on the metal matrix at the damaged part of the coating; placing a cover plate at the damaged part of the coating; transferring the test piece with the cover plate into an environmental test box, and setting temperature, humidity and test time; the test piece is moved out of the environment test box, washed, dried and photographed, the filiform corrosion length is measured, and the filiform corrosion risk of the plated steel is judged according to the filiform corrosion length. The method provided by the embodiment of the invention can shorten the test time.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention provides a circuit board test method and device based on a flying probe tester. According to the method, a test point set is determined by obtaining a design file of a circuit board, establishing an electrical connection model and identifying components and pins on the circuit board. And generating test combination set data by analyzing the conduction relationship between the test points, and further generating test scheme data. And based on the test scheme data, a test path is generated by using a path optimization algorithm, finally, the flying probe tester is used for testing, and a test report is generated according to a test result. The flying probe tester adopts the combination of an annular probe and a sharp needle probe, the annular probe is used for a pin connector to ensure accurate contact, and the sharp needle probe is used for other types of components to improve the test precision and adaptability. Compared with a traditional test method, the test scheme can be generated more efficiently, the test path can be optimized more efficiently, the test time is remarkably shortened, and the reliability and accuracy of circuit board testing are improved.

The invention provides a fuel cell bipolar plate coating life prediction method, and the method comprises the steps: determining a termination condition of a bipolar plate coating life test; based on the accelerated corrosion test platform and the simulated cathode potential of the fuel cell under the normal operation condition, performing an off-line real life test on the bipolar plate coating to obtain a first corresponding relation between the contact resistance and the real test time; adjusting a test condition, and performing an offline accelerated life test on the fuel cell bipolar plate coating to obtain a second corresponding relation between the contact resistance and the accelerated test time and a corresponding first accelerated test duration when the offline accelerated life test reaches a termination condition; obtaining a mapping relation between the real test time and the accelerated test time based on the first corresponding relation and the second corresponding relation; and obtaining a prediction result of the service life of the fuel cell bipolar plate coating based on the first acceleration test duration and a mapping relation between the real test time and the acceleration test time. The prediction accuracy is improved; and the prediction cost is reduced.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The invention relates to the technical field of valve detection, and discloses a multifunctional valve testing device and a use method.The multifunctional valve testing device comprises a water tank and a base installed in the middle of the water tank through two platforms, the two platforms are located in the middle of the front side and the middle of the rear side of the base respectively, and the base is provided with annular rails; the annular track is provided with a plurality of sets of fixing bases distributed at equal intervals, the annular track drives the multiple fixing bases to conduct fixed-distance conveying, the fixing bases circularly move around the end face of the base, and the positions of the fixing bases are switched in a reciprocating mode. The annular track can drive the fixed base to conduct fixed-distance conveying, so that the position of the workbench and the position of the multifunctional valve on the workbench can be automatically switched according to a set program. In the testing process, the valve can sequentially pass through a plurality of stations such as air inflation, water entry vibration, bubble detection and air pressure re-detection, the valve does not need to be manually and frequently carried, the testing efficiency is greatly improved, meanwhile, the detection time is prolonged, and the detection result is improved.

The invention provides an equipment reliability test profile generation method based on a quantitative acceleration test, and relates to the technical field of acceleration tests, and the method comprises the steps: obtaining a reliability index for target equipment, and carrying out the statistics of a test scheme; according to the reliability index and the statistical test scheme, determining the total conventional test time and the reference cycle index for the target equipment; determining an acceleration stress value corresponding to the target stress according to the working limit of the target equipment for the target stress; calculating an acceleration factor of the target stress according to a reference stress value and an acceleration stress value of the target equipment for the target stress; and according to the conventional test profile, the reference stress value, the reference cycle index, the acceleration stress value, the acceleration factor and the total conventional test time of the target equipment, a reliability acceleration test profile of the target equipment is generated, and the reliability acceleration test profile is used for performing a reliability acceleration test on the target equipment for the reliability index. Therefore, the universality of the test is improved, and the test time is shortened.

The invention discloses an MTBF accelerated identification test method suitable for a smart stadium machine room server, and the method comprises the steps: giving a qualitative conclusion for a plurality of key comparison factors of a new server and an existing server through similarity analysis, and carrying out the recognition of the new server according to the scoring result of an industry expert and the historical use time of the existing server; and obtaining the equivalent reliability test time of the server. Through an acceleration test method, after key environmental factors of the server are identified, conventional temperature cycle, vibration and temperature stress are converted into an equivalent acceleration stress profile based on an inverse power law, Arrhenius and a Cofen-Mansen model acceleration model, a reliability acceleration test is completed, and the equivalent reliability test time of the server is obtained. And completing MTBF lower confidence limit evaluation according to the equivalent reliability test time based on the similar product method and the equivalent reliability test time based on the accelerated test method, and judging whether the server passes a reliability identification test or not.

The present invention discloses an integrated circuit chip testing system based on an AI algorithm, which relates to the field of integrated circuit chip testing technology and includes a chip testing platform. The chip testing platform is communicatively connected to the following modules, including: a data acquisition module for collecting historical test data from existing integrated circuit chip testing equipment, preprocessing the data, and integrating the data to obtain a chip test data set; a model training and optimization module for analyzing the chip test data set, learning the relationship between chip performance and test vectors, and training a test vector AI optimization model. The present invention automatically generates optimized test vectors by analyzing historical test data, avoiding the redundant item-by-item test process in traditional testing, accurately locating key test nodes through the test vector AI optimization model, reducing unnecessary test steps, thereby significantly shortening test time and improving test efficiency.

The invention discloses an aircraft parallel collaborative test method, device and equipment and a storage medium, and the method comprises the steps: decomposing a total test process of a single aircraft, and obtaining a plurality of test items of the single aircraft; sorting the plurality of test items on the basis of the association and dependency relationship among the test items, and sorting the test items of the plurality of aircrafts in sequence on the basis of a sorting result to obtain a double-code network diagram of the plurality of aircrafts; based on the double-code network diagram, identifying a test item link with longest time consumption when a plurality of aircrafts are tested at the same time, so as to generate a critical path; and based on the established test process optimization model, optimizing all test items on the critical path by taking test time and test resources as optimization targets, and outputting an optimal parallel test scheme of the plurality of aircrafts. The aircraft test launching efficiency and the resource utilization rate can be effectively improved, the preparation time is shortened, and it is ensured that the test process is completed on time with high quality.

The invention belongs to the technical field of testability design of integrated circuits, and discloses a 3D IC MBIST test method based on an intelligent algorithm, and the method comprises the steps: carrying out the isomorphic grouping through analyzing the space coordinates, hierarchical affiliation and multi-dimensional attributes of a memory; establishing a three-dimensional layout relationship based on the improved interlayer distance model; the hierarchical clustering algorithm is adopted to merge memory clusters according to spatial proximity, and a grouping architecture with the minimum controller number is constructed; a dynamic test scheduling model is established in combination with a multi-target simulated annealing algorithm, and test time is optimized under power consumption constraint through a temperature attenuation mechanism. According to the method, three-dimensional collaborative optimization is carried out on spatial layout, time sequence constraint and power consumption budget, the contradiction between area overhead and test efficiency of a traditional memory built-in self-test scheme in a 3D IC is solved, and lamination test challenges under the condition that the test temperature is limited are effectively handled; and the test economy and reliability of the heterogeneous integrated chip are obviously improved.

The invention relates to a system testing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in the process of executing each test case of the distributed system, obtaining a call tree and a coverage rate of the test case, obtaining a case weight corresponding to the test case according to the coverage rate, clustering all the test cases according to the call tree to obtain multiple groups of clusters, and sending the multiple groups of clusters to the distributed system; and determining a test priority corresponding to each test case under each group of clusters according to the case weight, and carrying out regression testing on the distributed system based on the test priorities. By adopting the method, the distributed system can be tested more comprehensively and specifically, and the test time and resources are saved, so that the stability and reliability of the system are ensured.

The invention discloses a terminal communication test method and system based on an SQL database. The method comprises the following steps: determining test content; establishing a relation between the terminal and a computer with a preset SQL database through serial port communication, wherein a plurality of simulation meters of the SQL database are respectively used for simulating a plurality of electric energy meters; when multi-protocol analysis reply is carried out, received data frame protocols are distinguished and analyzed firstly and stored in a structural body, then the data frame protocols enter different processing function trees to be processed one by one, reply information frames are established, and finally information is replied through a serial port. Editing the running state of the simulation meter, and simulating the running state of at least one electric energy meter; and enabling the terminal to send a message of the collection task to each simulation table, or / and each simulation table to report timed freezing data or table data to the terminal. According to the invention, the test cost and the site demand are reduced, the test time is shortened, the test can be carried out quickly, conveniently and clearly, and the test efficiency is improved.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The embodiment of the invention discloses a multi-channel test method, electronic equipment and a test system thereof, and the method comprises the steps: receiving first identification information obtained by scanning of scanning equipment, and selecting a corresponding test channel according to the first identification information; the test channel is provided with a to-be-tested circuit board in advance; receiving second identification information obtained by scanning the to-be-tested circuit board by the scanning equipment; sending a test instruction to the test equipment on the corresponding test channel to enable the test equipment to test the to-be-tested circuit board according to a pre-configured test item to generate test data; and obtaining test data, and storing the test data according to the second identification information. By means of the mode, multi-channel parallel test preparation can be achieved, the test efficiency is improved, the overall test time is shortened, and therefore the test cost and human resource investment are reduced; and cloud storage and tracing of test data can be realized.

The utility model discloses a hydraulic drive type automatic dynamic penetration testing machine which comprises a base, a console and a lifting mechanism are arranged on the base, an automatic hammering device is arranged on the lifting mechanism, and the lifting mechanism and the automatic hammering device are both connected with the console through hydraulic pipelines. According to the utility model, the operating platform is adopted to regulate and control the working state of the lifting mechanism through pressure oil, so that the automatic hammering device can automatically lift and drop a hammer, the purpose of automatic hammering is achieved, the tedious process of manual operation is avoided, each hammering penetration depth can be recorded through the operating platform, the test time is effectively saved, the test efficiency is improved, and the test cost is reduced. And moreover, recording errors caused by manual counting of testers are prevented, the authenticity and accuracy of the test are ensured, the test efficiency is improved, and the device has the characteristics of convenience in installation, convenience in operation and the like.

The invention relates to a Modbus communication automatic test method and device of a controller, computer equipment, a storage medium and a computer program product. The method comprises the following steps: reading configuration parameters, and obtaining test connection parameters, test instance parameters of test contents and test time parameters; connecting with the tested controller according to the test connection parameters; generating test data according to the test instance parameters and the Modbus communication protocol content; sending test data to the tested controller according to the test time parameter, and executing a test by the tested controller according to the test data to obtain test result data; comparing the test result data with expected result data to obtain a test analysis result; and generating a test report according to the test analysis result. The method can improve the test coverage rate, efficiency and reliability.

The invention relates to a parallel test task scheduling method for a multi-target equipment distributed test system, and belongs to the technical field of scheduling methods. The invention provides a parallel test task scheduling method for a multi-target equipment distributed test system and aims to solve the problems that current equipment models are continuously increased, the number and complexity of equipment test tasks are obviously increased, a traditional test method is long in test time and low in resource utilization rate, and equipment test requirements at the current stage cannot be met. The method can obviously shorten the test time and improve the resource utilization rate, and comprises the following steps: step 1, describing an equipment parallel test task scheduling model by adopting a mathematical method; step 2, determining a constraint relationship of the test task on test time sequence and resources and a constraint condition satisfied between the test task and the test resources; 3, determining a fitness function corresponding to the test time and the resource utilization balance degree, and designing an overall fitness function; and step 4, solving the fitness function.

The invention belongs to the technical field of distributed control systems, and particularly relates to a stability test method and device for a static credible verification function of a credible DCS controller, and the method comprises the steps: obtaining a program and a configuration file needed in a stability test process of the DCS controller in a static state; obtaining a configuration mark state of the configuration file, and carrying out a stability test according to the program, the configuration mark state of the configuration file, the trusted module state of the static trusted verification function module and a corresponding operation result; obtaining a first test result and a second test result; and obtaining a first test result and a second test result corresponding to all the configuration strategies and the parameters according to the program, writing all the first test result and the second test result and the corresponding configuration strategies and parameters into a specified file, and generating a test report. According to the method, the credibility of comprehensive static credible verification is improved, the test time is shortened, and the test progress and quality are improved.

The embodiment of the invention provides a flash open block test method and related equipment thereof, and the method comprises the steps: obtaining a plurality of test samples of a flash open block, and selecting a plurality of test blocks from each test sample; carrying out a life early-stage data retention experiment on the plurality of selected test blocks, and obtaining the bit flipping number of each open case corresponding to the open block; a plurality of target open cases are selected from a plurality of open cases corresponding to the open block based on the number of bit flipping, and the plurality of target open cases are subjected to life middle and later period data retention experiments, so that the data retention performance of the open block is determined based on experimental data, the data retention performance of the open block can be rapidly and effectively evaluated, the test time of the 3D TLC flash memory is saved, and the test efficiency of the 3D TLC flash memory is improved. And the test conclusion is more stable and reliable.

The invention discloses a method and a system for improving chip parallel test DUT (Device Under Test) number, and belongs to the technical field of chip test. Comprising the following steps: performing peripheral circuit relay analysis according to a chip test schematic diagram; obtaining the number of digital input and output channels according to the digital board card configuration resources of the automatic test equipment; and according to the channel resources of the power board card of the automatic test equipment and the obtained number of the digital input and output channels, calculating to obtain the number of the tested chips of the parallel test. Compared with the prior art, the method has the beneficial effects that the whole test time is greatly shortened by optimizing the simultaneous test number of the tested chips, so that the test efficiency of the automatic test equipment is improved; due to the improvement of the test efficiency, the same number of chips can be tested in a shorter time, so that the use time and the labor cost of test equipment are reduced, and the batch test cost of the chips is further reduced.

The invention provides a bloom continuous casting machine withdrawal and straightening machine fault diagnosis method and system, and belongs to the technical field of bloom continuous casting machine withdrawal and straightening machine fault diagnosis. The fault diagnosis method comprises a single test and a single flow test, and three working modes of a soft reduction mode, a dummy ingot pressing mode and a hot blank pressing mode are set according to different working pressures of a withdrawal and straightening machine; judging whether the withdrawal and straightening machine is abnormal or not according to the displacement change and change speed of the withdrawal and straightening machine; according to the single-flow test, the withdrawal and straightening machines of the flow can be tested one by one in sequence, and the single-flow test is adopted to assist troubleshooting after abnormity is found, so that the test time is greatly saved, the problem that the hydraulic valve cannot be tested in a soft pressing mode is solved, the equipment abnormity is eliminated in the bud, the equipment failure rate is reduced, the equipment reliability is improved, and the test efficiency is improved. And the stable production sequence is ensured.

The invention provides a double-station radio frequency chip high-low temperature high-speed test sorting machine which comprises a test assembly, and the test assembly comprises a shell, a workbench, a preprocessor, a first air inlet pipe, a first exhaust pipe, a placing device and a detection table; the inner side wall of the shell is fixedly connected with a workbench, two preprocessors are symmetrically installed on the top of the workbench, the outer side walls of the preprocessors communicate with an air inlet pipe and an exhaust pipe, and the top of the workbench is symmetrically and fixedly connected with two detection tables. The chip is preprocessed through the preprocessor, it is ensured that the chip reaches the required test temperature before entering the detection table, and therefore the overall test time is shortened. The test cover slidably connected to the test bench facilitates rapid replacement of the test chip, and further improves the test speed. By adding the double testing stations, testing can be carried out alternately, two groups of chips can be tested at the same time, the waiting time is shortened, and the testing efficiency is improved.

The invention belongs to the technical field of testability design of super-large-scale integrated circuits, discloses a TSV test and diagnosis circuit and method based on BIST, and provides a hardware circuit architecture for TSV test and diagnosis. The device comprises a test access port controller, a test data register, a test vector generator, a shift register, a double-edge trigger, a TSV (Through Silicon Via) test controller, an improved loading chip packaging register and an improved capturing chip packaging register, and the test access port controller is responsible for configuring a test path, a test mode and a test enable signal; the TSV test controller is activated after the test enabling is synchronized by the double-edge trigger, and the improved chip packaging register based on the lossless compression structure is controlled to execute the test, so that efficient fault detection and diagnosis of different fault types are realized. Through cooperation of test vector generation and response compression, the test time is effectively shortened, and an innovative solution is provided for efficient and reliable TSV test and diagnosis.

The invention discloses a chip trimming function testing method and device, equipment and a medium, and relates to the technical field of chip testing. The method is applied to automatic test equipment and comprises the following steps: configuring a universal input / output interface for a to-be-tested chip; executing a chip test mode according to a test signal in the general input / output interface, and obtaining serial data sent by the automatic test equipment; and determining a data flow direction of the serial data according to a preset data format, and writing the serial data into a trimming register based on the data flow direction. According to the technical scheme, the test method can be simplified, and the test time can be shortened.

The invention relates to a TSN network minimization intrusive test scheduling method for guaranteeing production safety priority, which comprises the following steps: step 1, reservation of time-space isolated test resources: distributing a special test time slot with the lowest priority for test flow in a scheduling period of a centralized network controller; and step 2, a dynamic detection strategy of service awareness: monitoring key performance indexes of the key production service queue in real time, and when all the key performance indexes are lower than a preset threshold value, injecting test flow in a test time slot. And step 3, adaptive network optimization of closed loop feedback. According to the invention, on the premise of not influencing the normal operation of the key production service under the coal mine, the accurate and real-time monitoring of the TSN network state can be realized, the non-inductive test effect of the service is finally achieved, and the self-adaptive optimization capability is realized.