451 results about "Tests times" patented technology

The invention relates to the technical field of automation equipment, and discloses a three-temperature test sorting machine, which is characterized in that a heat preservation cover is arranged on a workbench, and a test space is formed by the heat preservation cover and the workbench, so that the consistency of temperature in the test space can be ensured, a chip is uniformly heated in the test space, and automation of three-temperature test of the chip is realized. The temperature of the chip is adjusted in advance by additionally arranging the pre-heating device, so that the whole chip is heated more uniformly, and meanwhile, the waiting time is fully utilized to adjust the temperature in advance, so that the test time is saved, the accuracy of a chip test result and the stability of a test yield can be ensured, and the test efficiency is improved. Moreover, the test efficiency is improved, and large-scale popularization and application are facilitated.

The invention provides a chip testing method and system, and relates to the technical field of chip testing. According to the invention, in response to a material receiving control instruction, the adsorption devices of the plurality of test assembly lines are controlled to alternately move to the feeding machine and adsorb the tested chips on the feeding machine, and then the adsorption devices are controlled to sequentially carry the tested chips to each carrying device; each carrying device is used for carrying the tested chip to the corresponding testing mechanism for functional testing, and finally, after testing of the tested chip is completed, the adsorption device is controlled to carry the tested chip to the discharging machine for discharging. According to the technical scheme, the adsorption devices of the multiple test assembly lines are controlled to alternately adsorb the tested chips and alternately discharge the tested chips, so that the waiting time of the feeding machine and the discharging machine can be shortened, feeding and discharging can be carried out without interruption, the test efficiency of the test system is improved, and the test time is saved.

The invention provides a vehicle body coating filamentous corrosion testing method which comprises the following steps: destroying a coating on the surface of a test piece, exposing a metal matrix, and cleaning chips on the surface of the test piece; introducing an electrolyte solution on the metal matrix at the damaged part of the coating; placing a cover plate at the damaged part of the coating; transferring the test piece with the cover plate into an environmental test box, and setting temperature, humidity and test time; the test piece is moved out of the environment test box, washed, dried and photographed, the filiform corrosion length is measured, and the filiform corrosion risk of the plated steel is judged according to the filiform corrosion length. The method provided by the embodiment of the invention can shorten the test time.

The invention relates to the technical field of wafer testing, and discloses a probe card and a testing system. The probe card comprises a plurality of unit groups which are periodically arranged; the unit group comprises at least two coaxial probes; wherein at least one coaxial probe is used for abutting against the input end of a to-be-tested device, and at least one coaxial probe is used for abutting against the output end of the to-be-tested device. According to the invention, through the plurality of unit groups arranged in the periodic array, a plurality of devices can be tested at a time when wafer testing is carried out, so that the wafer testing speed is improved, the wafer testing time is shortened, and the problems of low testing speed and long testing time existing in wafer testing in the prior art are solved.

The invention provides a memory testing device, a three-dimensional stacked memory chip, a memory testing method and a memory testing system, a built-in self-test (BIST) testing process, a first configuration register, a second configuration register and a third configuration register are embedded in the memory testing device, so that only specified testing excitation needs to be applied to a testing host, and the testing efficiency is greatly improved. According to the method, the corresponding functional parameters of the three-dimensional stacked memory chip can be automatically tested, and switching of the functional parameters, the test direction and the test mode can be realized only by adjusting the configuration values in the first configuration register, the second configuration register and the third configuration register during testing, so that the test process of the functional parameters of the memory is optimized, and the test efficiency is improved. And the test time and the test cost are greatly saved.

The invention provides an equipment reliability test profile generation method based on a quantitative acceleration test, and relates to the technical field of acceleration tests, and the method comprises the steps: obtaining a reliability index for target equipment, and carrying out the statistics of a test scheme; according to the reliability index and the statistical test scheme, determining the total conventional test time and the reference cycle index for the target equipment; determining an acceleration stress value corresponding to the target stress according to the working limit of the target equipment for the target stress; calculating an acceleration factor of the target stress according to a reference stress value and an acceleration stress value of the target equipment for the target stress; and according to the conventional test profile, the reference stress value, the reference cycle index, the acceleration stress value, the acceleration factor and the total conventional test time of the target equipment, a reliability acceleration test profile of the target equipment is generated, and the reliability acceleration test profile is used for performing a reliability acceleration test on the target equipment for the reliability index. Therefore, the universality of the test is improved, and the test time is shortened.

The present invention discloses an integrated circuit chip testing system based on an AI algorithm, which relates to the field of integrated circuit chip testing technology and includes a chip testing platform. The chip testing platform is communicatively connected to the following modules, including: a data acquisition module for collecting historical test data from existing integrated circuit chip testing equipment, preprocessing the data, and integrating the data to obtain a chip test data set; a model training and optimization module for analyzing the chip test data set, learning the relationship between chip performance and test vectors, and training a test vector AI optimization model. The present invention automatically generates optimized test vectors by analyzing historical test data, avoiding the redundant item-by-item test process in traditional testing, accurately locating key test nodes through the test vector AI optimization model, reducing unnecessary test steps, thereby significantly shortening test time and improving test efficiency.

The invention discloses an aircraft parallel collaborative test method, device and equipment and a storage medium, and the method comprises the steps: decomposing a total test process of a single aircraft, and obtaining a plurality of test items of the single aircraft; sorting the plurality of test items on the basis of the association and dependency relationship among the test items, and sorting the test items of the plurality of aircrafts in sequence on the basis of a sorting result to obtain a double-code network diagram of the plurality of aircrafts; based on the double-code network diagram, identifying a test item link with longest time consumption when a plurality of aircrafts are tested at the same time, so as to generate a critical path; and based on the established test process optimization model, optimizing all test items on the critical path by taking test time and test resources as optimization targets, and outputting an optimal parallel test scheme of the plurality of aircrafts. The aircraft test launching efficiency and the resource utilization rate can be effectively improved, the preparation time is shortened, and it is ensured that the test process is completed on time with high quality.

The invention belongs to the technical field of testability design of integrated circuits, and discloses a 3D IC MBIST test method based on an intelligent algorithm, and the method comprises the steps: carrying out the isomorphic grouping through analyzing the space coordinates, hierarchical affiliation and multi-dimensional attributes of a memory; establishing a three-dimensional layout relationship based on the improved interlayer distance model; the hierarchical clustering algorithm is adopted to merge memory clusters according to spatial proximity, and a grouping architecture with the minimum controller number is constructed; a dynamic test scheduling model is established in combination with a multi-target simulated annealing algorithm, and test time is optimized under power consumption constraint through a temperature attenuation mechanism. According to the method, three-dimensional collaborative optimization is carried out on spatial layout, time sequence constraint and power consumption budget, the contradiction between area overhead and test efficiency of a traditional memory built-in self-test scheme in a 3D IC is solved, and lamination test challenges under the condition that the test temperature is limited are effectively handled; and the test economy and reliability of the heterogeneous integrated chip are obviously improved.

The invention relates to a system testing method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: in the process of executing each test case of the distributed system, obtaining a call tree and a coverage rate of the test case, obtaining a case weight corresponding to the test case according to the coverage rate, clustering all the test cases according to the call tree to obtain multiple groups of clusters, and sending the multiple groups of clusters to the distributed system; and determining a test priority corresponding to each test case under each group of clusters according to the case weight, and carrying out regression testing on the distributed system based on the test priorities. By adopting the method, the distributed system can be tested more comprehensively and specifically, and the test time and resources are saved, so that the stability and reliability of the system are ensured.

The invention discloses a terminal communication test method and system based on an SQL database. The method comprises the following steps: determining test content; establishing a relation between the terminal and a computer with a preset SQL database through serial port communication, wherein a plurality of simulation meters of the SQL database are respectively used for simulating a plurality of electric energy meters; when multi-protocol analysis reply is carried out, received data frame protocols are distinguished and analyzed firstly and stored in a structural body, then the data frame protocols enter different processing function trees to be processed one by one, reply information frames are established, and finally information is replied through a serial port. Editing the running state of the simulation meter, and simulating the running state of at least one electric energy meter; and enabling the terminal to send a message of the collection task to each simulation table, or / and each simulation table to report timed freezing data or table data to the terminal. According to the invention, the test cost and the site demand are reduced, the test time is shortened, the test can be carried out quickly, conveniently and clearly, and the test efficiency is improved.

The invention discloses a method for realizing a redundant function memory chip test, which relates to the technical field of memory chip test, and comprises the following steps: calculating hyperedge coupling strength based on a hypergraph fault model, and generating a test vector sequence and a memory unit test instruction by adopting a weighted flipping mode according to the hyperedge coupling strength; injecting the test vector sequence into a tested memory chip, executing memory unit test instructions one by one, and capturing a failure unit coordinate and a failure mode category at the same time; constructing a Hall triad based on the failure unit coordinates and the failure mode category, executing theorem proving on the Hall triad by using a theorem proving device to verify the test completeness, generating an increment test vector when the verification fails, executing theorem proving again, and recording the result of the test completeness; according to the method, the hypergraph fault model is established, so that the coverage rate of non-independent faults is increased, the number of redundant test instructions is reduced, the test time and resource consumption are reduced, and the defect detection efficiency is improved.

The embodiment of the invention discloses a multi-channel test method, electronic equipment and a test system thereof, and the method comprises the steps: receiving first identification information obtained by scanning of scanning equipment, and selecting a corresponding test channel according to the first identification information; the test channel is provided with a to-be-tested circuit board in advance; receiving second identification information obtained by scanning the to-be-tested circuit board by the scanning equipment; sending a test instruction to the test equipment on the corresponding test channel to enable the test equipment to test the to-be-tested circuit board according to a pre-configured test item to generate test data; and obtaining test data, and storing the test data according to the second identification information. By means of the mode, multi-channel parallel test preparation can be achieved, the test efficiency is improved, the overall test time is shortened, and therefore the test cost and human resource investment are reduced; and cloud storage and tracing of test data can be realized.

The utility model discloses a hydraulic drive type automatic dynamic penetration testing machine which comprises a base, a console and a lifting mechanism are arranged on the base, an automatic hammering device is arranged on the lifting mechanism, and the lifting mechanism and the automatic hammering device are both connected with the console through hydraulic pipelines. According to the utility model, the operating platform is adopted to regulate and control the working state of the lifting mechanism through pressure oil, so that the automatic hammering device can automatically lift and drop a hammer, the purpose of automatic hammering is achieved, the tedious process of manual operation is avoided, each hammering penetration depth can be recorded through the operating platform, the test time is effectively saved, the test efficiency is improved, and the test cost is reduced. And moreover, recording errors caused by manual counting of testers are prevented, the authenticity and accuracy of the test are ensured, the test efficiency is improved, and the device has the characteristics of convenience in installation, convenience in operation and the like.

The invention relates to a parallel test task scheduling method for a multi-target equipment distributed test system, and belongs to the technical field of scheduling methods. The invention provides a parallel test task scheduling method for a multi-target equipment distributed test system and aims to solve the problems that current equipment models are continuously increased, the number and complexity of equipment test tasks are obviously increased, a traditional test method is long in test time and low in resource utilization rate, and equipment test requirements at the current stage cannot be met. The method can obviously shorten the test time and improve the resource utilization rate, and comprises the following steps: step 1, describing an equipment parallel test task scheduling model by adopting a mathematical method; step 2, determining a constraint relationship of the test task on test time sequence and resources and a constraint condition satisfied between the test task and the test resources; 3, determining a fitness function corresponding to the test time and the resource utilization balance degree, and designing an overall fitness function; and step 4, solving the fitness function.

The invention belongs to the technical field of distributed control systems, and particularly relates to a stability test method and device for a static credible verification function of a credible DCS controller, and the method comprises the steps: obtaining a program and a configuration file needed in a stability test process of the DCS controller in a static state; obtaining a configuration mark state of the configuration file, and carrying out a stability test according to the program, the configuration mark state of the configuration file, the trusted module state of the static trusted verification function module and a corresponding operation result; obtaining a first test result and a second test result; and obtaining a first test result and a second test result corresponding to all the configuration strategies and the parameters according to the program, writing all the first test result and the second test result and the corresponding configuration strategies and parameters into a specified file, and generating a test report. According to the method, the credibility of comprehensive static credible verification is improved, the test time is shortened, and the test progress and quality are improved.

The embodiment of the invention provides a flash open block test method and related equipment thereof, and the method comprises the steps: obtaining a plurality of test samples of a flash open block, and selecting a plurality of test blocks from each test sample; carrying out a life early-stage data retention experiment on the plurality of selected test blocks, and obtaining the bit flipping number of each open case corresponding to the open block; a plurality of target open cases are selected from a plurality of open cases corresponding to the open block based on the number of bit flipping, and the plurality of target open cases are subjected to life middle and later period data retention experiments, so that the data retention performance of the open block is determined based on experimental data, the data retention performance of the open block can be rapidly and effectively evaluated, the test time of the 3D TLC flash memory is saved, and the test efficiency of the 3D TLC flash memory is improved. And the test conclusion is more stable and reliable.

The invention provides a double-station radio frequency chip high-low temperature high-speed test sorting machine which comprises a test assembly, and the test assembly comprises a shell, a workbench, a preprocessor, a first air inlet pipe, a first exhaust pipe, a placing device and a detection table; the inner side wall of the shell is fixedly connected with a workbench, two preprocessors are symmetrically installed on the top of the workbench, the outer side walls of the preprocessors communicate with an air inlet pipe and an exhaust pipe, and the top of the workbench is symmetrically and fixedly connected with two detection tables. The chip is preprocessed through the preprocessor, it is ensured that the chip reaches the required test temperature before entering the detection table, and therefore the overall test time is shortened. The test cover slidably connected to the test bench facilitates rapid replacement of the test chip, and further improves the test speed. By adding the double testing stations, testing can be carried out alternately, two groups of chips can be tested at the same time, the waiting time is shortened, and the testing efficiency is improved.

The invention belongs to the technical field of testability design of super-large-scale integrated circuits, discloses a TSV test and diagnosis circuit and method based on BIST, and provides a hardware circuit architecture for TSV test and diagnosis. The device comprises a test access port controller, a test data register, a test vector generator, a shift register, a double-edge trigger, a TSV (Through Silicon Via) test controller, an improved loading chip packaging register and an improved capturing chip packaging register, and the test access port controller is responsible for configuring a test path, a test mode and a test enable signal; the TSV test controller is activated after the test enabling is synchronized by the double-edge trigger, and the improved chip packaging register based on the lossless compression structure is controlled to execute the test, so that efficient fault detection and diagnosis of different fault types are realized. Through cooperation of test vector generation and response compression, the test time is effectively shortened, and an innovative solution is provided for efficient and reliable TSV test and diagnosis.

The invention relates to a TSN network minimization intrusive test scheduling method for guaranteeing production safety priority, which comprises the following steps: step 1, reservation of time-space isolated test resources: distributing a special test time slot with the lowest priority for test flow in a scheduling period of a centralized network controller; and step 2, a dynamic detection strategy of service awareness: monitoring key performance indexes of the key production service queue in real time, and when all the key performance indexes are lower than a preset threshold value, injecting test flow in a test time slot. And step 3, adaptive network optimization of closed loop feedback. According to the invention, on the premise of not influencing the normal operation of the key production service under the coal mine, the accurate and real-time monitoring of the TSN network state can be realized, the non-inductive test effect of the service is finally achieved, and the self-adaptive optimization capability is realized.

The invention provides an in-situ monitoring immersed cooling liquid and server compatibility testing device and testing method. The device comprises an inner-layer shell, a server host, a cooling liquid circulation module, a ventilation module, a temperature control module, an electrical property sensor module, a data acquisition module and a control module. The temperature control module monitors and adjusts the temperature of the cooling liquid in real time, the test time is remarkably shortened, and the test efficiency is improved; the cooling liquid circulation, ventilation and temperature control module highly reduces the real service environment of the cooling liquid and the server host; the server host is used as a tested object and a control center and is responsible for automation of data acquisition, processing, display, recording and control, so that the automation degree is higher; a temperature measuring element and an electrical performance sensor in the temperature control module monitor the temperature and the electrical performance of the cooling liquid in real time and feed back data in time, so that problems can be found quickly and timely, meanwhile, the appearance state of the server host is observed, and the compatibility of the cooling liquid and the server is evaluated comprehensively.

The invention relates to the technical field of chip function testing, and particularly discloses a multi-site testing method for TOF sensor chip function testing, which comprises the following steps: completing hardware self-inspection and software loading; the host receives a'ready 'signal fed back by the sorting machine / probe station through GPIB communication, and confirms that each slave and the corresponding peripheral are in a'to-be-tested' state through TCP communication or Pipe interaction; the host issues an independent test instruction to each slave; after each slave receives the instruction, the corresponding test resource board card is controlled to provide a test condition for the chip to be tested, and the chip output data is collected at the same time; after completing the single-station test, each slave uploads a test result to the host; the host captures the test data from the corresponding network disk and counts the yield; and the host sends the final result of the multi-station test to the sorting machine / probe station through the communication driver and automatically grabs the next batch of chips to be tested. According to the method, the overall test time is greatly shortened through the multi-site parallel test.

The invention provides an ECU testing method and device and a first frame message testing system, and the testing method comprises the following steps: controlling the ECU to be powered on, synchronously starting a power-on timing function, and determining whether a first frame message sent by the ECU is received or not; when it is confirmed that the first frame of message is received, obtaining the current timing time; judging whether the test frequency reaches a preset test frequency or not; if the preset test frequency is not reached, controlling the ECU to be powered off, turning off the power-on timing function, and returning to the step of controlling the ECU to be powered on, synchronously starting the power-on timing function and detecting whether a first frame message sent by the ECU is received or not after the power-on timing function is turned off; and if the preset test frequency is reached, outputting the power-on first frame message outgoing time of the ECU based on the timing time obtained by each test. According to the ECU test method and device and the first frame message test system, the number of devices required by the test is small, the measurement precision is high, the process operation is simple, and the test efficiency is high.

The invention discloses a battery pack air tightness test method and a related device, complete air tightness test data can be obtained through incomplete air tightness test data of a battery pack and a corresponding mapping relation established in advance, the air tightness test time is saved, the battery pack production efficiency is improved, and the battery pack air tightness test efficiency is improved. And the investment of an airtight test cabinet can be reduced, and the cost is saved.

The invention discloses a test case execution method, electronic equipment, a storage medium and a program product, and relates to the technical field of testing, the explicit dependency relationship among test cases is identified according to a test case set, and the implicit dependency relationship among the test cases is identified according to historical execution data; according to the identification result of the explicit dependency relationship and the implicit dependency relationship, a dependency graph of the test case set is constructed, the dependency graph is constructed in a mode of combining the static test case set and the dynamic historical execution data, so that the constructed dependency graph is more accurate, and then the dependency type of the test case is determined according to the dependency graph. The execution sequence of the test cases in the test case set is determined according to the dependency types, so that different characteristics of the test cases of different dependency types are considered, the test efficiency is improved, tests are executed according to the execution sequence, invalid tests are prevented from being executed, the test time is shortened, and the test cost is reduced; the technical problems of low test efficiency and high test cost in related technologies are solved.

The invention relates to the technical field of circuit product testing, in particular to an integrated circuit product testing device and a method thereof.The integrated circuit product testing device comprises a first conveying belt, a testing table and a second conveying belt, a detection machine body is installed on the testing table, a probe is arranged on the lower end face of the detection machine body, and a bottom supporting plate is arranged below the probe; mounting plates are arranged on the front side and the rear side of the bottom supporting plate, an auxiliary conveying belt is arranged on the sides of the mounting plates, a Z-axis pressing strip is arranged on one side of the auxiliary conveying belt, a containing cavity for containing the bottom supporting plate is formed in the testing table, a group of lateral main clamping plates are rotationally mounted on each of the two horizontal sides of the bottom supporting plate, and pressing pieces are mounted on the lateral main clamping plates through detachable structures; according to the invention, the test of the integrated circuit product can be rapidly and continuously carried out, the manual intervention and the test time are obviously reduced, accurate positioning can be provided, and the circuit product is ensured to be located at the same test position during each test, so that the consistency and the reliability of the test are improved.

The invention discloses a high-temperature melt viscosity testing device and method, and the testing device comprises a testing box; a visual assembly is arranged on one side of the test box; an adjusting mechanism, wherein the test box and the visual assembly are arranged above the adjusting mechanism; collecting the change state of the material in the test box through the visual component, and calculating the viscosity of the material; image data of materials in the testing box can be monitored in real time through the visual assembly, the viscosity of the materials is calculated according to the change of size data, the testing box can control the temperature and atmosphere, the high-temperature melt viscosity in different testing environments can be conveniently adjusted, testing is easy and convenient, the sample preparation size is small, and the testing time is short.

The invention relates to a test time training method based on invariant graph learning, and the method comprises the following steps: 1, a joint training stage, a joint training encoder fg, a main task classification head pi m and self-supervision task classification heads pi s1 and pi s2 are trained through a graph classification task and an auxiliary self-supervision task by using marked training set data, and the joint training stage is divided into two parts including invariant graph recognition and multi-level graph comparison learning; step 2, in a test time training stage, realizing self-adaption of the model on test data by minimizing the difference of feature distribution of a training domain and a test domain; and step 3, a test stage: in a model test stage, carrying out specific processes and strategies of model evaluation and fine adjustment by using a test sample. According to the scheme, through a test time training method, the model is finely adjusted by using label-free test data distribution, and the generalization performance of the model in a distribution offset scene is improved.

The invention provides an enhancement method for a question answering system during testing based on reinforcement learning, and belongs to the technical field of natural language processing. The method aims at solving the technical problems that an existing large language model (LLM) faces knowledge blind areas, reasoning chain breakage and context length limitation in a question and answer (QA) task, an existing fine adjustment method is high in calculation cost and damaged in generalization ability, and a prompt strategy seriously depends on a limited context window and lacks long-term memory. The method comprises the following steps: firstly, collecting reflection experience through multiple attempts and a failure reflection mechanism, and constructing an experience library; thirdly, performing text embedding, clustering and semantic abstracting on experiences in the experience library, and constructing an external memory library; secondly, a memory selection process is formalized into a Markov decision process (MDP), reinforcement learning (such as a PPO algorithm) is used for training a strategy agent, and the agent is optimized with a current task as a state, with memory item selection as an action and with LLM answer correctness as a reward; finally, in a test time (inference) phase, the agent dynamically selects the most helpful memory entry according to the new task and integrates it into the hint of the LLM to generate a final answer. According to the method, under the condition that LLM internal parameters do not need to be updated, the question and answer accuracy is dynamically improved, the calculation overhead is reduced, and the limitation of a context window is effectively overcome.

The present invention relates to a test device for expanding a metal sheath, comprising a frame, a guide mechanism, a lifting plate, a first test cone, a first clamping mechanism and a first distance measuring sensor, wherein the frame comprises a first plate, the guide mechanism comprises a guide shaft and a guide sleeve, the guide shaft is arranged on the frame, and the guide sleeve is movably sleeved on the outside of the guide shaft, the guide sleeve is configured to move along the axial direction of the guide shaft, and the lifting plate moves in a controlled manner. The test device, by adopting the technical means of the guide mechanism, the first clamping mechanism and the first distance measuring sensor, can ensure that the metal sheath maintains coaxiality with the first test cone during the expansion test, and realizes real-time measurement of the expansion diameter through a laser beam, effectively solving the problems of inaccurate positioning, large measurement errors and long test time in the prior art, thereby achieving the technical effects of improving test accuracy, improving expansion consistency and shortening test time.