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35 results about "Tests times" patented technology

A hoof wear simulation test circuit and method

This invention discloses a shoe wear simulation test circuit and method. The shoe wear simulation test circuit includes at least an EBS controller, and the shoe wear simulation test method includes: acquiring the current test voltage, providing the current test voltage to the EBS controller, and receiving the current feedback signal output by the EBS controller; determining the current theoretical remaining wear of the shoe based on the current test voltage; determining the current tested remaining wear of the shoe based on the current feedback signal; and determining the current test result based on the current theoretical remaining wear and the current tested remaining wear. The technical solution of this invention can realize the simulation test of shoe wear detection function in a laboratory environment, with short test time and high accuracy, thus improving the reliability and safety of the braking system.
Owner:FAW JIEFANG AUTOMOTIVE CO

A press-pack IGBT sub-module test adapter and test equipment

The application provides a press-pack IGBT sub-module test adapter and a test device. The press-pack IGBT sub-module test adapter comprises a lower clamp. The lower clamp comprises: a conductive base plate, the conductive base plate having an array of positioning holes, the array of positioning holes comprising a plurality of separate positioning holes; a positioning assembly, the positioning assembly comprising a conductive adapter, the conductive adapter being adapted to be placed on the array of positioning holes, the conductive adapter being provided with a first recess, the first recess being adapted to place a to-be-tested sub-module; and a first fastener, the first fastener being adapted to penetrate the conductive adapter on the side of the first recess and extend in at least part of the positioning holes. When the structure of the to-be-tested sub-module changes, the structure of the whole adapter does not need to be redesigned, the universality of the adapter is improved, and thus the test cost is reduced and the test time is shortened.
Owner:GLOBAL ENERGY INTERCONNECTION RES INST CO LTD +2

Digital twin management method and system based on multi-source data fusion

PendingCN122347058ATest performanceMulti source data
The application relates to the technical field of material testing, and particularly relates to a digital twin management method and system based on multi-source data fusion. A test material is placed in a test environment with specified test conditions to collect multi-source monitoring data of the test material in the test environment. The multi-source monitoring data is fed back to a pre-established digital twin, and simulation data corresponding to various test conditions of the digital twin is recorded. The simulation data corresponding to various test conditions is arranged in a test time sequence to obtain test performance information flow of the digital twin. The material properties of the test material are analyzed based on the test performance information flow, and life cycle information flow of the test material in various working environments is constructed according to the analysis result.
Owner:GONGDA INTERNATIONAL ENGINEERING & DESIGN CO LTD LTD

A multi-station automatic qt testing device

PendingCN122141964ASortingTest efficiencyAutomatic test equipment
The application discloses a kind of multi-station automatic QT test equipment, belong to test equipment technical field, including base frame, assembly line, test piece conveying line, qualified piece conveying line, carrier disc backflow conveying line, defective product conveying line and lifting positioning transfer line assembly, the left end and right end of assembly line are respectively equipped with discharge mechanism and feeding mechanism, by above-mentioned mode, in the present application, feeding mechanism, discharge mechanism, test piece conveying line, qualified piece conveying line, carrier disc backflow conveying line and lifting positioning transfer line assembly constitute the circulation of carrier disc conveying, realize the automatic QT test of test piece, and multiple lifting positioning transfer line assembly and multiple multi-station test mechanism cooperate simultaneously to test piece conveying line on test piece take and place and test, and each multi-station test mechanism simultaneously tests multiple test pieces, reduces test time, significantly improves test efficiency, simultaneously, unqualified piece is placed on defective product conveying line and temporarily stored, waits subsequent processing.
Owner:SUZHOU YUNRUICHUANG AUTOMATION TECHNOLOGY CO LTD

A test method and test system applied to an AI accelerator platform

The present disclosure provides a test method and test system applied to an AI accelerator platform, according to available resource information, a plurality of task queues are divided, and available resource information is allocated to each task queue, which can ensure that resources are not preempted between task queues and conflicts are avoided. At the same time, according to the test completion of the task queue, the remaining available resource information is dynamically adjusted, which is beneficial to compress the total test time consumption and realize the optimal efficiency.
Owner:SPREADTRUM COMMUNICATION (SHANGHAI) CO LTD

A testing device and method for flexibility of a point blade connecting iron of an outside locking device

The present application relates to a kind of outside locking device point rail connecting iron flexibility test device and method, test device at least includes workbench (1), bottom plate (2), support plate (3), press bar (4), connecting block (5), lock block (6), sensor (11), man-machine interface (13), push-pull plate (17), point rail connecting iron (15) and the like component, fixed bottom plate (2) by supporting bolt (8) and press block (7) cooperation, press bar (4) is hinged with support plate (3) and connecting block (5) by pin (9)-1, pin (10)-2, sensor (11) is installed between connecting block (5) and lock block (6) and is connected with man-machine interface (13) signal, after push-pull plate (17) and point rail connecting iron (15) are fixed, form movable connection by bolt with lock block (6), connecting iron seat (16).The present application shortens test time, standardizes operation process, effectively improves test efficiency and result reliability, provides scientific support for product quality control.
Owner:XIAN RAILWAY SIGNAL

Efficient testing method for new energy vehicle power battery

The application discloses a kind of high-efficiency test methods of new energy automobile power battery, and it is related to battery test technical field.The method first decomposes complete test demand into multiple independent test subtasks;Then construct a non-complete series dynamic test workflow, preposition safety test and allow non-conflict task parallel execution;During the test process, the main control unit carries out real-time data-driven dynamic scheduling, terminates invalid test immediately when encountering failure, and optimizes subsequent task path according to measured data;Finally, automatically synthesize test report.The application overcomes the shortcomings of long traditional serial test cycle, low equipment utilization rate by parallelization, dynamic scheduling, can significantly shorten the total test time, improve test efficiency and intelligent level, realize early fault rapid filtration.
Owner:云动(太仓)测控技术有限公司

Simulation software testing method, computer device, storage medium and program product

The application relates to a simulation software testing method, a computer device, a storage medium and a program product. The method comprises the following steps: obtaining a test data set of simulation software; the test data set comprises at least one test data; the test data comprises layout extraction data and simulation configuration data; based on the test data, a test scene corresponding to the test data is determined; based on the test scene and the test data, the simulation software is tested to obtain at least one preliminary test result; and based on the preliminary test result of each test data, a test result of the simulation software is determined. The method can reduce test time consumption and improve test flexibility.
Owner:SEMITRONIX

Doc test method for virtual calibration post-processing model development

The application discloses a DOC test method for virtual calibration post-processing model development, and the experiment adopts a DOC test device which comprises a DOC, a DPF, a mixing section, SCR I and SCR II-ASC arranged in sequence along the airflow direction of exhaust gas; a first test module, a second test module and multiple thermocouples; the first test module is arranged upstream of the DOC and the SCR II-ASC; the second test module is arranged downstream of the DOC, the DPF, the mixing section and the SCR II-ASC; and the multiple thermocouples are arranged inside the DOC, the DPF, the SCR I and the SCR II-ASC. The DOC test method comprises the following steps: sensor position arrangement, which comprises the arrangement of the first test module, the second test module and the multiple thermocouples; DOC load step test; WHSC test; DOC light-off test; and WHTC test. By virtue of the method, the data obtained by testing can ensure the accuracy of the post-processing model of the virtual development platform, reduce the demand for sensors and other equipment, save test time and accelerate the model development of the virtual platform.
Owner:GUANGXI YUCHAI MASCH CO LTD

A test execution method for negative bias temperature instability test

This application discloses a test execution method for negative bias temperature instability testing, belonging to the field of semiconductor technology. Addressing the technical problem of long test times and the need for extrapolation in negative bias temperature instability testing of semiconductor devices, this application, based on the power-law lifetime model of semiconductor devices, maps the standard test conditions for negative bias temperature instability testing to rapid test conditions with faster decay rates and no need for heating by increasing the gate voltage amplitude. This reduces the test time and heating time for semiconductor devices in negative bias temperature instability testing, thereby accelerating the testing process. Furthermore, in the equivalent process, the degradation degree of the semiconductor device under rapid test conditions and the rapid test time is equivalent to the degradation degree that occurs when operating under standard test conditions to the target lifetime. This allows the test results to be directly used as the evaluation index of the device at the target lifetime after the test is completed, without the need for further derivation.
Owner:NEXCHIP SEMICON CO LTD

Pressure test flow configuration method and system, and pressure test method

ActiveCN115774671BSimulationTested time
The application provides a pressure test flow construction method for pressure testing of bank software, comprising the following steps: receiving a test time period, the test time period comprising a plurality of test dates; calculating a reference time period according to the test time period, the reference time period comprising a plurality of reference dates, and each reference date corresponding to a test date; collecting flow of the bank software on each reference date in the reference time period as historical flow; constructing a construction factor; and calculating target flow of the test date according to the historical flow and the construction factor, the pressure test flow comprising target flow of all test dates. In addition, the application also provides a pressure test flow construction system, a computer device and a pressure test method. The pressure test flow construction method provided by the application can efficiently construct pressure test flow closer to reality.
Owner:PING AN BANK CO LTD

A probe contact-based memory chip ft test method

The application relates to the technical field of semiconductor testing, and discloses a memory chip FT test method based on probe contact. The method comprises the following steps: acquiring wafer-level process parameters, layout and wiring topology and historical yield data of a chip; dividing a logic test block; calculating defect probability scores of each block and sorting to generate a test sequence; performing full-function testing in sequence, collecting response signal features in real time and comparing the response signal features with a health benchmark model, and dynamically triggering adjacent expansion testing or failure determination; and feeding back test results to update yield data. The application shortens the test time and reduces the test cost while guaranteeing the defect coverage rate through a risk-oriented adaptive test strategy.
Owner:SHENZHEN ZHOUHONG SEMICONDUCTOR TECHNOLOGY CO LTD

A diode production conductivity testing device

The utility model relates to diode testing arrangement technical field discloses a conductivity test equipment for diode production, including test board, the test board one side surface is nested and is equipped with the universal meter, the test board upper surface transversely is equipped with the adjusting groove, the adjusting groove upper surface both ends are slid respectively and are equipped with first test head and second test head, first test head and second test head all include sliding seat, test chamber, motor piece and connecting sliding block, the adjusting sliding groove upper surface both sides are slid and are equipped with sliding seat, the sliding groove inboard and corresponding position all are equipped with test chamber, the utility model can realize diode and universal meter positive and negative pole quick steady butt joint, can depend on diode size accurate adjustment test head spacing, promotes the test applicability and efficiency, can protect the test structure simultaneously in the non - test time, prolongs its life, guarantees the test result accurate.
Owner:MAANSHAN SHICHEN SEMICON TECH CO LTD

Automated production scheduling method and device for harmonic reducer

PendingCN122366978AData setState switching
This application discloses an automated production scheduling method and apparatus for harmonic reducers, relating to the field of industrial control technology. The automated production scheduling method for harmonic reducers includes: acquiring a basic dataset for multi-station testing of the harmonic reducer; optimizing the test item set corresponding to the test samples to determine the target test sequence of the test samples and the target test time corresponding to the target test sequence; constructing an initial test scheduling scheme for multi-station testing based on the target test sequence and target test time; and solving the initial test scheduling scheme to obtain the target test scheduling scheme for the harmonic reducer. Because the test sequence of the test item set corresponding to the test samples is optimized, unnecessary station state switching waiting time is reduced; and by further solving the initial test scheduling scheme, the global optimality of the obtained solution is ensured, improving production efficiency and equipment utilization.
Owner:SHENZHEN KOMO INNOVATION ROBOTICS TECHNOLOGY CO LTD

A memory testing method, device, workstation and storage medium

This application provides a memory testing method, apparatus, workstation, and storage medium, relating to the field of testing technology. The method includes: displaying a task settings interface during normal operating system operation; determining that the slot identifier displayed by the user based on the task settings interface is the slot to be tested in the test task, and determining the number of tests set by the user for the test task; sending the identifier of the slot to be tested to the BIOS firmware through the operating system kernel driver, so that the BIOS firmware disables the non-test slot; in response to the BIOS firmware disabling the non-test slot, running a specified test script; after the specified test script finishes running, checking whether the number of runs of the specified test script has reached the number of tests for the test task; if not, returning to the step of running the specified test script. This solution enables memory testing of memory modules inserted in specific slots without repeatedly inserting and removing memory modules.
Owner:SUMA TECH CO LTD

A method, system, device, and storage medium for constructing a skin creep compliance

PendingCN122350647Areduce system errorreduce distractionsStructural engineeringTested time
The application belongs to the field of biomechanical test data processing, and discloses a skin creep compliance construction method, system, device and storage medium. The method performs negative pressure suction test on the tested skin, obtains test parameters and original displacement-time data of the tested skin in the test process; identifies a test starting point, a creep starting point and a test termination point according to the change of the displacement of the tested skin with the test time; determines a compensation factor based on the displacement change amount from the test starting point to the test termination point and the displacement change amount from the creep starting point to the test termination point; compensates the displacement value of the tested skin based on the test parameters and the compensation factor, and obtains a creep compliance sequence according to a nonlinear calculation relationship.
Owner:XI AN JIAOTONG UNIV

A method and system for implementing loopback testing based on algorithm switching

The application provides a method and system for realizing loopback test based on algorithm switching. The method does not require external equipment, and one key can complete the whole process of transmission, collection and analysis. The method can realize integrated self-loopback, reduce operation difficulty, greatly reduce test time, and improve test efficiency. The method uses FPGA dynamic reconfiguration, supports multiple test scenes through algorithm switching, improves test controllability and integration, and reduces hardware cost.
Owner:BEIJING AEROSPACE MEASUREMENT & CONTROL TECH

SNN single sample test time adaptive method based on heuristic verification and risk gating

PendingCN122366539ASingle sampleRisk indicator
The application discloses a self-adaptive method for SNN single-sample test based on heuristic verification and risk gating. The method is aimed at the problems that single-sample updating in unlabeled test stream is easily misled by noise, and internal activity of the spiking neural network is easy to go to the extreme and cause performance decline. Before each sample enters, the model parameters, buffer and random state are snapped, and the calculation group, verification group and review group are generated to enhance the view. First, the baseline consistency and risk indicators are established by the verification group, and when the abnormality occurs, the robust configuration is switched and restarted. When the baseline is stable, only the update direction of the updateable parameter subset is calculated once, the small step heuristic update is executed, and the gating screening is performed. Through the rear, the final step length that meets the yield and safety conditions is screened from the candidate step length set, and the independent acceptance view is retested. After outputting the recognition result, the snapshot is unconditionally restored to block the cross-sample accumulation, which is used for online robust calibration in deployment inference.
Owner:HOHAI UNIV

Method and system for generating test sequences for electronic controllers

PendingCN122110955AVehicle testingError detection/correctionTest efficiencyElectronic controller
The application provides a test sequence generation method and a test system of an electronic controller. The method comprises the following steps: obtaining a plurality of test items of the electronic controller and a dependency relationship and a mutual exclusion relationship between the plurality of test items. Receiving a test resource required by each test item in the plurality of test items. Generating a test sequence according to the dependency relationship, the mutual exclusion relationship and the test resource required by each test item. Thus, the test sequence generation method and the test system of the electronic controller provided by the application can shorten the test time of the ECU, improve the test resource utilization rate and the test efficiency.
Owner:FULIAN PRESION ELECTRONICS (TIANJIN) CO LTD

Parallel interface test method, system and device

The embodiment of the invention discloses a parallel interface testing method, system and device. A sampling point sequence corresponding to a to-be-tested parallel interface is determined, a target sampling point needing to be processed currently is determined in the sampling point sequence, a data transmission test is executed on the to-be-tested parallel interface based on a target time sequence parameter and a target reference voltage corresponding to the target sampling point, and the number of error codes in the data transmission test process is recorded. And when the number of the error codes reaches a preset threshold value, determining the target sampling point as a failure point, stopping the data transmission test on the target sampling point, and testing the next sampling point. Therefore, by setting the preset threshold value, the next sampling point is directly tested when the number of the error codes reaches the preset threshold value, the testing time of a single sampling point can be shortened, and the testing efficiency of the parallel interface can be improved.
Owner:PINGTOU GE (HANGZHOU) SEMICON CO LTD

Automotive domain controller automated testing method and apparatus, electronic device, and medium

The application provides an automobile domain controller automatic test method, device, electronic equipment and medium, the method obtains a pre-built domain controller test system, a pre-defined domain controller test action, a pre-defined domain controller test parameter, controls a test action execution device to execute the pre-defined domain controller test action, and monitors the data parameter in the pre-defined domain controller test action execution process through a test parameter monitoring device, compares the pre-defined domain controller test parameter with the data parameter monitored by the test parameter monitoring device, obtains a parameter comparison result, and judges whether the domain controller test passes according to the parameter comparison result; the application can reduce the test time and improve the test efficiency by not needing to spend a lot of learning time to train a mechanical arm to simulate user actions.
Owner:CHONGQING CHANGAN TECH CO LTD

Chip package reliability accelerated test and life prediction method based on multi-physics coupling

The application discloses a multi-physical field coupling chip package reliability accelerated test and life prediction method, which comprises the following steps: first, a temperature cycle-vibration-humidity-power cycle-thermal shock-electromagnetic radiation field five-dimensional integrated stress test environment is constructed, and each stress parameter is accurately set and applied according to the actual working condition; then, a five-dimensional accelerated test model is established by weighting and fusing each single stress acceleration model, and the weight coefficient is determined based on the actual working condition influence weight; subsequently, finite element simulation is adopted to analyze the stress, heat conduction and electromagnetic coupling effect of the packaging structure, and the acceleration factor is corrected in real time by combining the physical failure (PoF) algorithm; finally, a packaging level life digital image containing failure modes and failure time distribution is constructed based on multi-dimensional data, and reliability test and life prediction are realized. The test time is less than or equal to 200 hours, the life prediction accuracy is greater than or equal to 90%, and the method is suitable for mainstream packaging types such as BGA, CSP, SiP and FlipChip, thereby providing an efficient solution for chip package reliability evaluation.
Owner:CHINA ELECTRONICS STANDARDIZATION INST HUADONG BRANCH

Multi-station rapid test tension equipment

ActiveCN224471413UInductorTested time
The utility model discloses a kind of multi-station rapid test tension equipment, it is related to spoke test technical field, including workbench, and at least 2 tension test mechanisms being set on workbench;The tension test mechanism includes tension inductor, first limiting unit, second limiting unit and drive unit;First limiting unit has the first limiting through slot for placing spoke rod and limiting spoke cap, second limiting unit has the second limiting through slot for placing spoke rod and limiting spoke cap;First limiting through slot and second limiting through slot are substantially located on the same horizontal plane;The drive unit is used to drive the first limiting unit relative to the second limiting unit close or away, and the tension inductor is set in first limiting unit or second limiting unit to obtain the real-time tension data of spoke.Sufficiently utilize the test time of tension test mechanism, worker continuously carries out feeding and discharging, realize rapid feeding and discharging, significantly improve the efficiency of spoke tension test.
Owner:XIAMEN XINGAOJING COMPOSITE MATERIALS TECHNOLOGY CO LTD

A test device for a nuclear power plant reactor protection system

PendingCN122266833APower plant safety arrangementElectrical measurement instrument detailsNuclear plantProcess engineering
The application relates to a channel precision, response time and protection setting value automatic testing device of a nuclear power plant reactor protection system based on a NASPIC platform, and particularly relates to a nuclear power plant reactor protection system testing device. Field instruments or sensors are simulated, signals are injected into a NASPIC platform safety level DCS system port, corresponding output signals of the safety level DCS system are collected, data of a safety level DCS engineer station are acquired, comparison or logical operation is carried out, and a corresponding test report is generated. The application realizes a reactor protection system regular test automatic testing technology based on the NASPIC platform, can greatly shorten a test time, improve work efficiency and reduce human errors.
Owner:CNNC LONGYUAN TECH CO LTD +1

Electromigration test structure, test structure and method of testing thereof

An electromigration test structure, a test structure, and a test method thereof are disclosed. The electromigration test structure includes: a stacked metal layer under test (UTP) and a signal metal layer. Along the extension direction of the UTP, the signal metal layer is located at both ends of the corresponding UTP and is electrically connected to both ends of the corresponding UTP. Multiple via structures are located between the UTP and the signal metal layer. In this embodiment, because there are multiple via structures between the UTP and the signal metal layer, compared to a scheme where the UTP and the signal metal layer are electrically connected through a single via structure, the probability of thermal damage caused by current passing through the via structure is reduced. Therefore, when applying current to the signal metal layer for wafer-level reliability testing, a large current can be applied to the signal metal layer, correspondingly shortening the test time, thereby improving test efficiency and the reliability of the electromigration test structure.
Owner:SEMICON MFG INT TIANJIN +2

A device for improving the voltage resistance test efficiency of an RJ45 cable assembly by parallel method

ActiveCN224500823UImprove Hipot Test EfficiencyImprove work efficiencyTested timeControl theory
The utility model discloses a device of parallel method improves RJ45 cable assembly pressure resistance test efficiency, including a plurality of point position knob switch, main knob switch, a plurality of RJ45 connector interface and a plurality of banana head interface, through the point position of RJ45 interface parallel connection to corresponding knob switch, realize a test many products, significantly reduce test time.
Owner:SICHUAN AEROSPACE LIAOYUAN SCI & TECH CO LTD