Low-power-consumption and low-leakage SRAM applied to storage and calculation integrated chip

Abstract

The invention discloses a low-power-consumption and low-leakage SRAM applied to a storage and calculation integrated chip. The low-power-consumption and low-leakage SRAM comprises: an SRAM storage operation unit array which comprises N rows and M columns of storage operation units, wherein each storage operation unit comprises a storage module and an operation module and is used for realizing voltage signal input, storing input data in the storage module and calculating and outputting the data by the operation module; a ground wire voltage raising module which is used for raising the voltage of the power supply ground wire of the selected column in the SRAM storage operation unit array so as to improve the writing threshold value of the full-selection unit when the SRAM writes data; and abit line charge recovery module which is used for recovering the leakage charge of the bit line of the half-selection unit when the SRAM writes data so as to drive the ground line voltage lifting module, reducing the voltage of the bit line of the half-selection unit and improving the static noise margin of the half-selection unit. According to the invention, the arithmetic logic unit is integrated into the SRAM, so that the design of the storage and calculation integrated chip is realized.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a low-power consumption and low-leakage SRAM applied to an integrated storage and calculation chip. Background technique [0002] The Von Neumann computer system architecture separates the arithmetic unit from the memory and uses a bus structure to communicate. As the semiconductor process node enters the deep sub-micron level, the von Neumann structure will be limited by the transmission bandwidth of the bus structure, so that applications such as cloud computing, artificial intelligence and neural networks will be limited by the performance and functionality of the traditional von Neumann structure. consumption bottleneck. [0003] In order to overcome the above-mentioned bottleneck, the memory-computing integrated chip that integrates the memory and the arithmetic unit can directly use the data output by the memory for calculation, reducing the additional po...

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Problems solved by technology

[0004]Since SRAM occupies the main area of ​​the memory-computing chip, SRAM seriously affects the power consumption of the memory-computing chip

At this stage, the power consumption of SRAM is mainly reduced by reducing the power supply voltage. However, the reduction of power supply voltage will reduce the read and write performance of SRAM and make it difficult to drop the power supply voltage of SRAM. The leakage charge of the bit line on the selected cell will increase the power consumption of the SRAM during operation

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