254 results about "Indium phosphide" patented technology

A package includes a bridging element (an OMIB), and first and second photonic paths, forming a bidirectional photonic path. The OMIB has first and second interconnect regions to connect with one or more dies. Third and fourth unidirectional photonic paths may couple between the first interconnect region and an optical interface (OI). A photonic transceiver has a first portion in the OMIB and a second portion in one of the dies. The first and the second portions may be coupled via an electrical interconnect less than 2 mm in length. The die includes compute elements around a central region, proximate to the second portion. The OMIB may include an electro-absorption modulator fabricated with germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs). The OMIB may include a temperature compensation for the modulator.

The invention relates to the technical field of chip packaging, in particular to an indium phosphide chip packaging device which comprises a chip clamp, a spot welding head, a hot welding head, a cold welding head, a testing mechanism and a conveying belt, a plurality of supporting frames are sequentially arranged on the outer side of the conveying belt, electric push rods are installed on the supporting frames, and the output ends of the electric push rods are fixedly connected with connecting plates; the conveying belt is arranged to be the chain plate conveying belt, the packaging and positioning mechanism is installed on the fixing block, the packaging and positioning mechanism can position the chip module while conveying the chip module, and meanwhile, when spot welding, hot welding and cold welding packaging are sequentially carried out on indium phosphide chips on the chip module, the chip module can be subjected to spot welding, hot welding and cold welding packaging at the same time; and through mutual cooperation with the press-down cooperation mechanism, the effect of accurately positioning the indium phosphide chip on the chip module during packaging is further realized, the chip module is prevented from deviating from the initial position due to intermittent conveying of the conveyor belt, and the indium phosphide chip packaging efficiency of the chip module is further ensured.

The invention relates to the technical field of general control systems, in particular to an abnormity monitoring method for an indium phosphide crystal growing furnace, which comprises the following steps: analyzing the operation condition of the growing furnace based on the growth operation data of the growing furnace, and then analyzing the condition of the growing furnace by combining the operation condition of the growing furnace and the internal growth environment data, meanwhile, the growth state of the indium phosphide crystal is analyzed based on the growth state data of the indium phosphide crystal in the growth furnace, the growth quality of the indium phosphide crystal is estimated according to the analysis result of the condition of the growth furnace and the analysis result of the growth state of the indium phosphide crystal obtained through analysis, and a big data analysis mode is adopted; the growth furnace condition analysis result and the growth state analysis result of the indium phosphide crystal are analyzed in real time, so that the growth quality of the crystal is accurately estimated in real time, and the growth quality of the indium phosphide crystal and the monitoring safety are improved.

The invention belongs to the field of lasers, and discloses a growth method for reducing laser Ith through N grating burying, which subversively adopts an N-type grating structure, uses a built-in P-N junction formed by the N-type grating structure and a subsequent P-type buried layer as a natural and efficient current blocking layer, and structurally eliminates a current leakage path. Afterwards, in the heating stage, trace arsine is introduced to carry out atomic-scale protection on the sensitive grating morphology, at the optimal mass transport temperature, the high mobility characteristic of indium atoms is utilized to carry out shape-preserving filling on grating grooves, flawless preliminary planarization is achieved, and through variable-temperature thickening growth and high-temperature annealing in the pure phosphorus atmosphere, the high-temperature-resistant grating is obtained. And performing quality optimization and defect repair on the buried layer and the key interface. The series of linked steps ensure that the indium phosphide buried layer with flat atomic scale and complete crystal lattice can grow on the fragile N-type grating, and ensure that a high-quality covering layer and an active region grow on the N-type grating.

Aspects disclosed in the detailed description include an impure Indium Phosphide (InP) semiconductor substrate. Related apparatus and methods are also disclosed. In this regard, in some exemplary aspects disclosed herein, a semiconductor substrate comprising a silicon layer and an impure InP layer adjacent to the silicon layer. The impure InP layer may be epitaxially grown on a Silicon (Si) nanoridge base or directly bonded to the silicon layer after being epitaxially grown and cleaved. Utilizing an impure InP layer advantageously provides structural strength to be deployed in a 300 millimeter wafer process while achieving the electrical and thermal characteristic of InP it provides in a semiconductor substrate.

The invention relates to the technical field of crystal growth control, in particular to an indium phosphide single crystal growth temperature control method based on a sensor network, which comprises the following steps of: importing temperature control data and atmosphere control data into a temperature-gas interaction state analysis model; analyzing the interaction state of the growth temperature and the growth atmosphere in the indium phosphide single crystal growth process; the diffraction structure data are imported into an indium phosphide single crystal structure state analysis model, and the structure state of the indium phosphide single crystal is analyzed; and according to the interaction state analysis result of the growth temperature and the growth atmosphere and the structure state analysis result of the indium phosphide single crystal, constructing an indium phosphide single crystal quality prediction model, and predicting the quality of the indium phosphide single crystal. According to the quality prediction result of the indium phosphide single crystal, the growth temperature of the indium phosphide single crystal is optimized, deviation and fluctuation in the growth process can be effectively reduced, uniform distribution of temperature and atmosphere pressure is ensured, and then the uniformity and integrity of the indium phosphide single crystal are improved.

The invention discloses an indium phosphide single crystal growth dynamic thermal field control method based on AI calibration of multiple temperature zones, and relates to the technical field of semiconductor material preparation and artificial intelligence control. According to the method, a multi-temperature-zone thermal field digital twin model is constructed, multi-channel temperature data, heating power data and crystal growth image data in an indium phosphide single crystal growth furnace are collected, and real-time three-dimensional reconstruction of thermal field distribution in the furnace is carried out; with the crystal growth rate, the solid-liquid interface shape and the thermal stress distribution as optimization targets, power adjustment instructions of heaters in all temperature zones are output; an AI calibration module is introduced to correct thermophysical parameters of the digital twin model; deducing a thermal field state at a future moment, compensating a thermal hysteresis effect in advance, and realizing accurate closed-loop control of an indium phosphide single crystal growth process; according to the invention, the problem that the traditional PID control is difficult to cope with nonlinear, strong-coupling and large-lag thermal field change in large-size crystal growth is solved, and the single crystal yield and the lattice quality are remarkably improved.

The invention relates to an indium phosphide crystal containing sulfur and tin, a single crystal wafer, a preparation method of the indium phosphide crystal and the single crystal wafer and a device. Specifically, the invention relates to an indium phosphide crystal which is an N-type indium phosphide crystal, and the indium phosphide crystal contains 0.5 ppm to 500 ppm of sulfur and also contains 0.5 ppm to 1000 ppm of tin. The invention also relates to a method for preparing the indium phosphide crystal doped with sulfur and tin and a device prepared by using the indium phosphide crystal. The indium phosphide crystal doped with sulfur and tin obtained according to the invention has the advantages of low dislocation density, few defects and high yield.

The invention discloses a silicon-based indium phosphide laser and a preparation method thereof, and relates to the technical field of semiconductor devices, the silicon-based indium phosphide laser comprises a silicon substrate, a composite insulating layer, a Van der Waals buffer layer and an indium phosphide epitaxial structure which are stacked in sequence; the indium phosphide epitaxial structure comprises a first epitaxial structure stacked on the Van der Waals buffer layer and a second epitaxial structure stacked on the first epitaxial structure; the first epitaxial structure at least comprises a lower cladding layer, a lower limiting layer, a lower waveguide layer, a spacing layer, a multi-quantum well active region, an upper limiting layer, an etching stop layer, an upper waveguide layer and an upper cladding layer which are sequentially stacked, a Bragg grating is manufactured in the upper waveguide layer, and the second epitaxial structure comprises a regrowth cladding layer and a contact layer which are sequentially stacked; the Van der Waals buffer layer is a two-dimensional material film, and the problems of lattice mismatch, thermal expansion coefficient mismatch and polarity structure difference of integration of the silicon substrate and the InP epitaxial layer are thoroughly solved from a physical mechanism by introducing the single-layer two-dimensional material Van der Waals buffer layer.

Described herein are optoelectronic devices and methods incorporating strain balanced direct bandgap AlxIn1-xP multiple quantum wells. The described devices are strain balanced in that the net strain between the ordered quantum wells and barriers is low, or in some cases zero. Advantageously, the described devices may be specifically designed for higher efficiency than existing AlxIn1-xP and may be grown on commercially available GaAs substrates.

Provided are an apparatus and a method for manufacturing indium phosphide crystals by vertical temperature gradient solidification. The apparatus includes a furnace body, a crucible, a centrifugal motor, and an injection system. During synthesis, the crucible is rotated to bring the melt in the crucible into close contact with the side wall of the crucible under the action of centrifugal force, and bubbles are injected into a position close to the side wall of the crucible of the metal melt. After the synthesis is completed, the vertical temperature gradient is controlled to end single crystal growth.

Disclosed in the present invention are a reaction device for narrow-band luminescence indium phosphide quantum dots, and a method for producing narrow-band luminescence indium phosphide quantum dots using the reaction device. The reaction device comprises a high gravity device and a photothermal device, wherein the high gravity device comprises a housing, an electric motor, a rotating disk, shear packing, a liquid distributor, a reaction chamber, a packing cover, a gas outlet, a liquid outlet and liquid inlets; and the photothermal device comprises a laser heating device, a circuit and water cooling device, a reflective layer and a laser controller. In the present invention, infrared laser is coupled into a high gravity reactor, and solvent media such as water or organic compounds are used to absorb infrared light and convert same into thermal energy to raise the temperature of the high gravity reactor, so as to initiate a nucleation reaction of a reactant precursor in a "micro-droplet reactor", thereby realizing the controllable growth of quantum dots in the micro-droplet reactor; and then nanoparticles of uniform size are finally obtained by means of controlling the laser irradiation and heating duration.

The invention belongs to the technical field of solar cells, and discloses a flexible silicon substrate-indium phosphide solar cell and a preparation method thereof. The flexible silicon-based indium phosphide solar cell comprises a lower electrode, a flexible silicon solar cell, a first transparent conductive layer, a conductive adhesive, a second transparent conductive layer and an indium phosphide solar cell which are sequentially stacked from bottom to top, an antireflection film layer and an upper electrode are arranged on the indium phosphide solar cell; the conductive adhesive is obtained by dispersing polymethyl methacrylate microspheres coated with metal on the surface into an EVA solution. Heterogeneous integration is achieved through the transparent conductive adhesive, the two-end laminated cell is formed, the device is light, thin and flexible, the defects that a traditional four-end laminated cell is rigid, heavy, large in optical loss and the like are overcome, and the solar cell has good performance.

Disclosed herein are avalanche photodiodes (APDs) particularly useful for high-sensitivity Geiger-mode APDs formed using an array of micro-cells. The photodetector is formed on a semiconductor substrate of indium phosphide (InP) having epitaxial layers, including indium gallium arsenide (InGaAs) as the photodetecting layer, with n-doped InP to one side, and layers of InP incorporating p-doped regions on the opposite side. The p-doped regions may serve to define an array of micro-cells, which may be arranged in a hexagonal pattern. A well may be etched through the epitaxial structures, allowing an electrode that contacts the n-doped InP layer and another that contacts the p-doped InP regions to be patterned on the same side of the detector. Flip-chip bonding techniques can then attach the semiconductor wafer to a stronger support substrate, which may additionally be configured with electronic circuitry positioned to electrically contact the electrodes on the semiconductor wafer surface.

A semiconductor optical device includes: a lower mesa structure extending in a stripe shape and composed of some layers including an active layer; a buried layer configured to bury both sides of the lower mesa structure and made of indium phosphide; and an upper mesa structure extending in a stripe shape and composed of some layers including a bottom layer made of phosphorus-free materials, the bottom layer having a bottom surface protruding from a topmost layer of the lower mesa structure, the bottom surface being in contact with the lower mesa structure and the buried layer.

The application provides a method for evaporating and atomizing corrosion of an indium phosphide wafer, comprising the following steps: A) placing the indium phosphide wafer to be corroded into a rotating disc, and adding a corrosion solution into a corrosion tank; the rotating disc is arranged in a closed space above the corrosion tank, and the closed space and the corrosion tank are connected through a valve channel; the corrosion solution comprises hydrogen peroxide, sulfuric acid, phosphoric acid and hydrochloric acid; B) hot nitrogen gas is introduced into the corrosion tank to evaporate and atomize the corrosion solution, and the valve channel is opened to allow the atomized corrosion solution to enter the closed space above; C) the rotating disc is started to rotate the wafer, and the indium phosphide wafer on the rotating disc is corroded; D) the corroded wafer is taken out and cleaned to obtain the corroded indium phosphide wafer. Compared with the method of liquid phase corrosion in the prior art, the present process has the advantages of higher wafer corrosion amount, simpler operation, higher automation degree and more uniform corrosion compared with the traditional corrosion process.

Provided is an indium phosphide substrate, a method for manufacturing an indium phosphide substrate, and a semiconductor epitaxial wafer, which can suppress the occurrence of contamination of the surface of the indium phosphide substrate caused by residues in the edge portion. An indium phosphide substrate, wherein the indium phosphide substrate has an edge portion including at least a surface having a curvature, and wherein, with respect to the surface roughness of the edge portion, each of the measured values of the root mean square height Sq calculated using a laser microscope and applying an L filter with a cutoff wavelength of 20 μm at a plurality of positions on the entire surface of the edge portion is 0.15 μm or less.

This invention relates to a highly efficient automated splicing system for indium antimonide short crystal rods, belonging to the field of semiconductor material processing technology. Specifically, it relates to a highly efficient bonding and slicing technology for multiple short crystal rods of indium antimonide, indium phosphide, and other materials. The system includes a crystal rod conveying unit, a crystal orientation and size measurement unit, a splicing planning module, a buffer plate selection and adhesive application unit, and a crystal rod posture adjustment and bonding unit. This system achieves full automation from crystal rod loading to long rod assembly unloading. One operator can simultaneously manage three machines, requiring only periodic material replenishment; this reduces labor requirements by more than 80% compared to traditional manual splicing.

A device, method, and hybrid computing architecture for a Symbolic Photonic Logic Gate (SPLG) system that performs data processing primarily in the optical domain. The system comprises a photonic substrate, including silicon-photonics, indium phosphide, or similar optically active materials, patterned with optical waveguides and interferometric structures configured to implement logic operations through controlled optical interference, phase modulation, or non-linear optical effects. The SPLG system is configured to execute Boolean and symbolic logic functions without requiring intermediate optical-to-electrical signal conversion. In operation, information is encoded into one or more optical parameters including phase, polarization, wavelength, or amplitude, and processed within a Symbolic Optical Core optimized for linear algebraic operations such as matrix multiplication and vector transformation. The architecture further comprises an electronic control layer configured to initialize, configure, and monitor the photonic logic elements while allowing the majority of computational operations to occur within the optical domain, thereby reducing electrical interconnect congestion and resistive heating relative to fully electronic processors.

The present invention discloses a reaction device and method for narrow-band luminescent indium phosphide quantum dots. The reaction device comprises a hypergravity device and a photothermal device. The hypergravity device comprises a housing, a motor, a turntable, a shear filler, a liquid distributor, a reaction chamber, a filler cover, a gas outlet, a liquid outlet, and a liquid inlet. The photothermal device comprises a laser heating device, a circuit and a water cooling device, a reflective layer, and a laser controller. The present invention couples an infrared laser into a hypergravity reactor, utilizes a solvent medium such as water or organic matter to absorb the infrared light and convert it into heat energy to increase its temperature, stimulates the nucleation reaction of a reactant precursor in a "micro-droplet reactor", realizes the controllable growth of quantum dots in the micro-droplet reactor, and finally obtains nanoparticles of uniform size by controlling the laser irradiation and heating time.

The invention belongs to the technical field of crystal growth, and provides a growth method of a large-size semi-insulating indium phosphide single crystal. According to the VGF growth method of the indium phosphide single crystal, a thermal field structure is optimized, six temperature zones are set, and the temperature of each temperature zone is controlled; the method comprises the following steps: preparing an indium phosphide polycrystalline column, then charging and doping, respectively placing dopants in at least three axial partitions of the indium phosphide polycrystalline column, regulating the temperature before crystal growth, firstly regulating the temperature of an equal-diameter region, then regulating the temperature of a head seed crystal region, carrying out crystal growth, and respectively controlling the specific growth rates of seeding, shouldering, equal-diameter and ending stages; and finally, annealing to prepare the indium phosphide single crystal with the size greater than or equal to 6.5 inches. According to the invention, the preparation of the large-size semi-insulating indium phosphide single crystal with high quality and high yield is realized.

The invention discloses a bonding structure and a bonding method, the bonding structure comprises a silicon substrate and an epitaxial structure bonded on the silicon substrate, the epitaxial structure comprises an indium phosphide substrate, and an intrinsic indium phosphide layer, a P-type indium phosphide layer, a zinc layer and a zinc oxide layer which are sequentially arranged on the surface of one side, facing the silicon substrate, of the indium phosphide substrate, the zinc oxide layer is bonded on the surface of one side, facing the indium phosphide substrate, of the silicon substrate, and a doped element of the P-type indium phosphide layer is a zinc element. According to the invention, convenient integration of the indium phosphide material and the silicon substrate is realized, and the development of the indium phosphide-based silicon optical device is further promoted.

The present disclosure relates to the technical field of optoelectronics, and in particular to a resonance-enhanced mesa-type photodetector based on a chirped Bragg reflector. The photodetector comprises: a high-reflectance structure on a P-type ohmic contact layer, a P-type epitaxial layer, a graded doping absorption layer, an annular metal electrode on an N-type ohmic contact, an N-type epitaxial layer, a chirped Bragg reflector, and a semi-insulating indium phosphide substrate, which are sequentially formed from top to bottom.

The invention relates to the technical field of semiconductor materials, and particularly discloses an atomization cleaning method for an indium phosphide wafer. The atomization cleaning method comprises the following steps that an indium phosphide wafer rotating at a constant speed is sequentially subjected to atomization cleaning through a first acid solution and deionized water and then subjected to nitrogen purging drying; carrying out atomization cleaning with an alkaline peroxide solution and deionized water, and then carrying out nitrogen purging drying; and finally, carrying out atomization cleaning by using a second acid solution and deionized water, and carrying out nitrogen purging drying to obtain the clean indium phosphide wafer. According to the method, based on an acid-alkali-acid three-step synergistic mechanism, full-spectrum pollutant removal of oxides, organic matters, particles and metal ions is realized; the indium phosphide wafer rotating at a high speed can immediately strip reaction products and waste liquid through centrifugal force, and secondary adsorption is avoided; the technical defects that a traditional RCA wet cleaning process is prone to corroding the wafer, the surface roughness of the wafer is degraded, and secondary pollution is caused are effectively overcome.

The invention discloses a high-speed high-precision frequency modulation continuous wave laser ranging chip, which belongs to the technical field of laser ranging and comprises a laser light source module, an outer resonant cavity linear frequency modulation module, a coherent detection module and a signal processing module. The laser light source module adopts an indium phosphide DFB laser with an optimized multi-quantum well structure to generate narrow-linewidth tunable seed laser; the outer resonant cavity linear frequency modulation module realizes injection locking through a multi-micro-ring cascade resonant structure, suppresses nonlinearity in combination with an FPGA closed-loop correction unit, and outputs a high-linearity frequency modulation signal; the coherent detection module receives and transmits signals through an antenna and completes coherent frequency mixing. And the signal processing module realizes time sequence synchronization based on the correlation function, and calculates the target distance and speed through the frequency modulation continuous wave principle. The chip realizes frequency modulation bandwidth greater than or equal to 1.5 THz, sub-millimeter ranging precision and data acquisition rate greater than or equal to 1000 times / s, solves the contradiction between narrow linewidth and wide tuning, adapts to scenes such as intelligent driving and unmanned aerial vehicles, and gives consideration to integration level and reliability.

Provided is an indium phosphide single crystal substrate having a main surface. The indium phosphide single crystal substrate contains a dopant. The diameter of the main surface is 150-303 mm. The dislocation density in the main surface is 100 cm-2 or less. When the concentration of the dopant at the center of the main surface is a first concentration and the concentration of the dopant at the outer edge of the main surface is a second concentration, the value obtained by dividing by the first concentration the absolute value of the value obtained by subtracting the second concentration from the first concentration, is less than 10%.

The invention relates to a sodium dichloroisocyanurate composite polishing solution capable of improving indium phosphide removal rate and surface quality. The polishing solution is prepared from the following components: nano silicon dioxide with the concentration of 8.0 to 12.0 weight percent, an oxidant with the concentration of 0.8 to 1.1 weight percent, a complexing agent with the concentration of 0.8 to 1.1 weight percent, a surfactant with the concentration of 200 to 500 ppm and the balance of deionized water, and the pH value of the polishing solution system is 8.9-9.1. The oxidizing agent is sodium dichloroisocyanurate; the complexing agent is potassium sorbate; according to the polishing solution, the removal rate and the surface quality of indium phosphide are obviously improved, and harmful gas is not generated to the maximum extent under the alkaline condition.

The utility model discloses a fixing assembly for indium phosphide crystal heating, and relates to the technical field of indium phosphide crystal heating and fixing.The fixing assembly for indium phosphide crystal heating comprises a supporting seat, a placing groove is formed in the supporting seat, the three ends of the placing groove are open, an adjusting assembly is arranged in the placing groove, and the adjusting assembly is connected with the supporting seat. The fixing assemblies are arranged on the two sides of the top end of the supporting seat correspondingly, the moving grooves are formed in the upper surfaces of the two ends of the supporting seat correspondingly, the limiting grooves are formed in the inner walls of the two sides of the moving grooves correspondingly, each adjusting assembly comprises an adjusting frame and a moving part, and the connecting grooves are formed in the surfaces of the two ends of each adjusting frame correspondingly. The moving part is located on one side of the connecting groove, the moving part comprises a connecting base, and a connecting block is arranged at one end of the connecting base, and according to the scheme, the problems that most of existing indium phosphide crystals are directly placed together for heating, accumulation is likely to be caused, and consequently heating is uneven are solved.

The present invention relates to the technical field of indium phosphide polycrystal preparation, and specifically to a method and device for preparing indium phosphide polycrystal, comprising a support base, wherein a carrying plate is fixedly connected to the upper surface of the support base, a connecting mechanism is arranged at the middle position of the inner wall of the bottom end of the carrying plate, a loading and unloading mechanism, an immersion mechanism, a flushing mechanism and a drying mechanism are sequentially distributed on the inner wall of the bottom end of the carrying plate in a circumferential array, an auxiliary mechanism is arranged on the inner wall of the bottom end of the carrying plate, and a carrying mechanism for loading indium phosphide tailings for processing is arranged. Through the circumferential arrangement of the loading and unloading mechanism, the immersion mechanism, the flushing mechanism and the drying mechanism, when preparing indium phosphide polycrystal, multiple processing steps can be gradually cycled, so that multiple processing steps of the indium phosphide tailings are continuously performed, thereby improving the preparation efficiency of indium phosphide polycrystal and reducing the length of time for connecting multiple processing steps.

The indium phosphide single-crystal substrate has a circular main surface, and the main surface is virtually divided with a square grid at a grid interval of 1 mm. The square grid is composed of a plurality of grid points present along a first direction and a second direction orthogonal to the first direction. A set consisting of dislocation densities measured at the respective grid points has a first whole-surface mean as the mean of the set and a first whole-surface standard deviation as the standard deviation of the set, and each of the dislocation densities is classified as any one of a first level, a second level, and a third level. The grid points each determined to have a dislocation density classified as the second level are present in a region between an outline of a first square region and an outline of a second square region.