Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The method comprises the following steps of: providing a semiconductor substrate; forming a pseudo-gate region and side walls of the pseudo-gate region on the semiconductor substrate; forming epitaxial layers on the semiconductor substrate on the two sides of the pseudo-gate region to form source and drain regions, wherein the epitaxial layers are made of metal silicide, metal germanide or metal silicon germanide; forming interlayer dielectric layers to cover the epitaxial metal silicide layers of the source and drain regions; removing the pseudo-gate region to form an opening; and forming a gate dielectric layer on the inner walls of the opening, and forming a metal gate electrode on the gate dielectric layer to fill the opening. Before a substitute gate is formed, the epitaxial layers are formed on the semiconductor substrate on the two sides of the gate region and cover the whole source and drain regions of a Schottky barrier field effect transistor device, and the height of a Schottky barrier between the epitaxial source and drain regions and a channel is effectively reduced, so that the source and drain parasitic resistance of the device is obviously reduced, and the performance of the device is improved.

Description

technical field [0001] The present invention relates to semiconductor manufacturing technology, more specifically, to a semiconductor device and its manufacturing method. Background technique [0002] With the rapid development of semiconductor technology, the feature size of semiconductor devices is shrinking continuously, which makes the integration level of integrated circuits higher and higher, which also puts forward higher requirements for the performance of devices. [0003] At present, the research on the manufacturing process of CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) can be roughly divided into two directions, namely, the front gate process and the gate replacement process. Before, it will affect the gate oxide layer, and after the device size is continuously reduced, it will affect the electrical characteristics of the device, and the gate of the gate replacement process (gate last process, Gate Last) is in the source and drain F...

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Problems solved by technology

[0004] However, although the gate-last process of CMOSFET reduces the impact of gate oxide layer changes on device performance, it increases the source / drain parasitic resistance

refer to figure 1 , figure 1 For the COMSFET formed for the gate-last process, after the replacement gate stack 100 is formed, a contact hole is opened in the interlayer dielectric layer 110, and a metal silicide 120 is formed in the contact hole, and between the metal silicide 120 and the spacer 102 If no metal silicide is formed, it will greatly increase the parasitic resistance of the device and affect the performance of the device

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