Semiconductor structure and forming method thereof

A technology of semiconductor and gate structure, applied in the field of semiconductor structure and its formation, can solve problems such as poor performance of fin field effect transistors, and achieve the effects of improving performance, suppressing short-channel effect, and reducing contact resistance

Active Publication Date: 2019-05-28
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the performance of fin field effect transistors prepared by the prior art is still poor

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] As mentioned in the background, FinFETs have poor performance.

[0034] figure 1 and figure 2 It is a schematic diagram of the structure of a fin field effect transistor.

[0035] Please refer to figure 1 and figure 2 , figure 2 yes figure 1 A schematic sectional view along line A-A1, figure 1 yes figure 2 A schematic cross-sectional view along the line B-B1, a substrate 100 with a gate structure 101 on it; source and drain doped regions 102 located in the substrate 100 on both sides of the gate structure 101; located on the substrate 100 and the gate structure 101 The above dielectric layer 103 has a contact hole 104 exposing the source-drain doped region 102 in the dielectric layer 103 .

[0036] In the above structure, with the continuous improvement of the integration degree of semiconductor devices, the size of the source-drain doped region 102 is continuously reduced, so that the subsequent contact area between the plug in the contact hole 104 and the ...

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Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a first region; forming a first gate structureand a first source-drain doped region located in the substrate at two sides of the first gate structure on the substrate with the first region, wherein the first source-drain doped region has first doped ions, and the first doped ions in the first source-drain doped region have a first atomic percentage concentration; and after the first gate structure and the first source-drain doped region areformed, forming a first improvement layer at the top of the first source-drain doped region, the first doped ions in the first improvement layer have a second atomic percentage concentration, and thesecond atomic percentage concentration is greater than the first atomic percentage concentration. According to the semiconductor device formed by the method, the contact resistance between the first source-drain doped region and the subsequently formed plug can be reduced, and meanwhile, the short-channel effect can be inhibited.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, the fabrication of semiconductor devices is constrained by various physical limits due to the pursuit of high device density, high performance, and low cost in semiconductor processes and progress to nanotechnology process nodes. [0003] Manufacturing and design challenges as CMOS devices continue to shrink have prompted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). Compared with the existing planar transistors, the fin field effect transistor has more superior performance in terms of channel control and reducing...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/06
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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