Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes: a gate electrode formed on a silicon substrate; source / drain regions formed at both sides of the gate electrode in the silicon substrate; and a silicide layer formed on the source / drain regions. The silicide layer includes a first silicide layer mainly made of a metal silicide having a formation enthalpy lower than that of NiSi and a second silicide layer formed on the first silicide and made of Ni silicide.

Description

BACKGROUND OF THE INVENTION [0001] (1) Field of the Invention [0002] The present invention relates to semiconductor devices and methods for fabricating the same, and particularly relates to a structure of a silicide layer and a method for forming the silicide layer. [0003] (2) Description of the Related Art [0004] In general metal oxide semiconductor (MOS) transistors, reduction of parasitic resistance such as contact resistance and wiring resistance is important in increasing operation speed. The reduction of parasitic resistance in such transistors is generally achieved by siliciding upper portions of source / drain regions and upper portions of gate electrodes. [0005] To increase the integration degree of a large-scale semiconductor integrated (LSI) circuit device, reduction of the vertical size as well as the horizontal size is needed. As a technique for reducing the vertical size, the junction depth of a doped layer to be source / drain regions needs to be reduced. However, if the ...

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Benefits of technology

[0009] It is therefore an object of the present invention to form an excellent Ni silicide layer by achieving both stable formation of a NiSi layer, which is a low-resistance layer, and reduction of the interface resistance generated at the interface between NiSi and silicon.

[0020] According to the present invention, a silicide layer containing a metal silicide having an enthalpy of formation (formation enthalpy) lower than that of NiSi is provided, i.e., a silicide layer having a lattice constant different from that of silicon is provided, at the interface between silicide and silicon, so that generation of NiSi2 forming an inverted-pyramidal silicide-silicon interface caused by lattice-constant matching with silicon is suppressed. Accordingly, the NiSi layer serving as a low-resistance layer is stabilized. In addition, the provision of a silicide layer including a metal silicide having a formation enthalpy lower than that of NiSi at the interface between silicide and silicon reduces the Schottky barrier height between silicide and silicon that is proportional to the formation enthalpy. Accordingly, the interface resistance between silicide and silicon that is proportional to the exponential function of the Schottky barrier height is reduced. In this manner, both stable formation of a NiSi layer as a low-resistance layer and reduction of the interface resistance at the interface between NiSi and silicon are achieved, so that an excellent Ni silicide layer is formed. Accordingly, a semiconductor device capable of being miniaturized and operating at high speed is implemented.

[0021] As described above, the present invention relates to semiconductor devices and methods for fabricating the same. In applications to semiconductor integrated circuit devices including silicide layers, for example, miniaturization and increase of the operation speed are achieved, and thus the present invention is very useful.

Problems solved by technology

However, it is reported that in the case of forming an alloyed silicide with the foregoing conventional techniques, coexistence of different elements in a silicide layer causes alloy scattering, resulting in increase of resistance (see, for example, non-patent literature 6: F. M. d'Heurle et al., “Resistivity of the solid solutions (Co—Ni)Si2”, J. Appl. Phys. 59, 1986, pp.

The interface resistance generated at the interface between NiSi and silicon serves as parasitic resistance that effectively increases the resistances of a silicide layer and a source / drain doped layer located under the silicide layer, resulting in causing deterioration of transistor performance.

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