Semiconductor device and manufacturing method

Abstract

The invention provides a manufacturing method of a semiconductor device. The method comprises the steps of forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer having a first work function over the capping layer, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gatefrom the treated portion of the metal layer having the second work function. The method of the invention provides a simple single metal layer with economic benefit to ensure that NMOS and PMOS devicerespectively have N type metal work function and P type metal work function, so gate patterning NMOS and PMOS devices are simple. The method can is compatible with prior CMOS technique manufacturingflow, so the semiconductor device can be easily integrated with the prior manufacturing processing equipment.

Description

technical field [0001] The present invention relates to a semiconductor device, and in particular to a method for manufacturing a semiconductor device in a high dielectric constant / gate metal manufacturing process. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in successive generations of IC production, each with smaller and more complex circuits than the previous generation. However, these advances have also increased the complexity of the IC manufacturing process, so the same progress is required in the IC manufacturing process to achieve a more advanced integrated circuit IC manufacturing process. [0003] In the course of IC innovation, functional density (ie, the number of interconnected devices per wafer area) has generally increased, while geometric size (ie, the smallest element or line that can be created in a manufacturing process) has a...

AI Technical Summary

Problems solved by technology

While this approach may be suitable for certain applications, it may not be suitable for all applications

For example, when NMOS and PMOS devices have complex gate stacks, it can greatly increase the difficulty of patterning gate stacks

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