45results about How to "Adjust Threshold Voltage" patented technology

The invention discloses a thin film transistor on the basis of metal oxide and a preparation method and application thereof. The preparation method comprises the following steps of: (1) making a buffer layer; (2) depositing a gate metal layer on the buffer layer; (3) preparing a gate insulation layer on the gate metal layer by using an anodic oxidation method, wherein the part in the gate metal layer, on which an oxide film does not need to be deposited, is protected by using a photoresist; (4) removing the photoresist; (5) removing an unrequired metal lead; (6) preparing an active layer on the gate insulation layer; and (7) according to the designed thin film transistor structure, depositing and patterning source and drain electrodes, a pixel electrode and a protection layer or an etched barrier layer. According to the invention, pure Al or Al alloy is used as gate metal and the gate insulation layer is prepared by using the anodic oxidation method. The performance of the gate insulation layer can be changed by regulating the components of the gate metal, so that the electrical properties of the thin film transistor are improved.

The invention provides a depletion type power semiconductor device and a manufacturing method thereof. The device comprises a semiconductor substrate, an epitaxial layer of a first doping type, a well region of a second doping type, an inversion layer of the first doping type, a gate dielectric layer and a gate electrode. The well region of the second doping type is formed on the epitaxial layer which is positioned on the semiconductor substrate, the second doping type is opposite to the first dope type, the inversion layer of the first doping type is arranged on the surface of the well region, and the gate dielectric layer and the gate electrode are sequentially positioned on the epitaxial layer. The distance of the well region extending below the gate electrode is 0.75XXj+b, wherein Xj refers to the junction depth of the well region, and b is larger than or equal to -2 micrometers and smaller than or equal to 5 micrometers. The depletion type power semiconductor device and the manufacturing method thereof are simple in process procedure, low in cost and high in threshold voltage controllability.

The invention provides a semiconductor device and a formation method thereof. The formation method of the semiconductor device comprises steps: providing a substrate, wherein the surface of the substrate is provided with an interlayer dielectric layer, a groove is arranged in the interlayer dielectric layer, and the surface of the substrate is exposed by the groove; forming a gate dielectric layer which covers the bottom and sidewalls of the groove; forming a first barrier layer which covers the gate dielectric layer; performing non-crystallization processing on the first barrier layer to convert the first barrier layer to a second barrier layer; and forming a metal layer which covers the second barrier layer, wherein the surface of the metal layer is aligned with the surface of the interlayer dielectric layer. According to the semiconductor device and the formation method thereof, the performance of the semiconductor device is improved.

The invention relates to a composite grid field effect transistor. Wherein, the grid, source, leak and substrate form the main body; the insulated layer is between grid and substrate; the groove is on the substrate between source and leak; the source extends shallow source extending area at the left end of groove; the grid extends shallow leak extending area at the right end; the invention is characterized in that the grid is composite grid and multi-crystal grid, while the left and right parts are different in conductive types; the left grid toward to source is P-type multi-crystal grid, while the left part toward leak is N-type multi-crystal grid. The invention can obtain radio MOSFET driving current, transconductance and cut-off frequency, and release the maximum field strength, thermal electronic effect and short-groove effect at the end of leak drift area.

The invention provides an MOSFET (metal oxide semiconductor field effect transistor) and a manufacturing method thereof. The MOSFET comprises a semiconductor substrate, a first insulating buried layer on the semiconductor layer, a back gate formed in a semiconductor layer on the first insulating buried layer, a second insulating buried layer on the first semiconductor layer, source/drain areas formed in a second semiconductor layer on the second insulating buried layer, a gate on the second semiconductor layer, and electric connection for the source/drain areas, the gate and the back gate. The back gate is located in one of the source/drain areas and below a groove area and not located below the other one of the source/drain areas. The electric connection includes a common conductive channel of the back gate and the source/drain areas. The short-channel channel inhibition effect is improved by the aid of the asymmetrical back gate of the MOSFET, and the area of a chip is reduced by the common conductive channel.

The invention provides a gate forming method comprising the steps of forming a single doped metal work function adjustment layer on a gate dielectric layer to enable a target work function to be between the metal work function layer and a work function of doped particles, and forming other gate layers on the metal work function adjustment layer. Through the method, the threshold voltage can be adjusted easily, the process is simple and can be implemented without multiple metal gate layers, and the manufacturing cost is reduced.

A method for forming an MOS transistor comprises providing a substrate; forming a back gate electrode, a back gate dielectric layer, a body region, a first functional layer and a front gate dielectric layer sequentially from the bottom surface of the substrate, the first functional layer being used for increasing the rate of migration of a carrier in a channel region; etching the front gate dielectric layer and the first functional layer and forming a first groove exposing a portion of the body region; conducting ion implantation on the first groove along the body region to form a heavily doped region; filling a metal layer in the first groove and forming a plug connected with the heavily doped region; and forming a second functional layer and a front gate on the surface of a front gate dielectric layer between the heavily doped regions sequentially from the bottom to the top, the second functional layer being used for reducing the leakage current of the channel region. The method for forming the MOS transistor can adjust the threshold voltage of the formed MOS transistor, improve the compatibility and matching rate of each MOS transistor in semiconductor devices and improve the performance of formed semiconductor devices.

The invention provides a gate medium structure of an MOS ( Metal-Oxide-Semiconductor) device, which comprises a boundary layer film formed on the surface of a semiconductor substrate and at least two layers of insulating films formed on the surface of the boundary layer film, wherein each of the at least two layers of insulating films has element components and concentrations, which are different from that of other adjacent insulating films, the boundary layer film and the at least two layers of insulating films are processed by an optimized annealing process, and the optimized annealing process is related to the element components and the concentrations of the boundary layer film and the at least two layers of insulating films so as to realize ideal distribution of the element components and the concentrations. In the invention, the gate medium structure of the MOS device is formed by depositing multiple layers of different material components or different concentrations of films in a certain order, and then, the ideal distribution of all element components and the concentrations in the gate medium structure is realized by the optimized annealing process.

The invention relates to a method for forming a semiconductor device, comprising the following steps: providing a semiconductor substrate; carrying out first ion doping and second ion doping to form a well region and a threshold voltage regulation region disposed in the semiconductor substrate, wherein the threshold voltage regulation region is disposed on the surface of the well region; forming a semiconductor epitaxial layer on the surface of the semiconductor substrate after the formation of the well region and the threshold voltage regulation region; and forming a transistor on the surface of the semiconductor epitaxial layer, wherein the channel region of the transistor is formed by the semiconductor epitaxial layer. According to the method for forming a semiconductor device, the semiconductor epitaxial layer, as the channel region of the transistor, avoids lattice damage caused by ion doping. Moreover, the semiconductor epitaxial layer used for forming the channel region is not doped or is lightly doped with boron. Thus, carrier scattering is reduced, the carrier migration rate of the transistor is high, and the device performance is superior.

The regulator suitable for memory array with several flash memory units, each of which includes one control grid, one floating grid, one source and one drain. The regulator includes one drain power source, constant current source and control grid source. The drain power source provides one positive voltage to the drain of the flash memory unit, the constant current source provides a source current to the source of the flash memory unit, and the control grid source provides a gradually raised grid voltage to the control grid of the flash memory unit to control the source current to the flashmemory unit and gradually change the critical voltage value of the flash memory unit.

Disclosed is a formation method of a semiconductor device. The method comprises: providing a semiconductor substrate, and forming an isolation structure in the substrate, wherein the isolation structure isolates the substrate to a first active area and a second active area, and the types of the first active area and the second active area are opposite; forming a high-k dielectric layer and a conducting layer on the high-k dielectric layer on the substrate, defining the conducting layer disposed in the first active area as a first conducting layer, and defining the conducting layer disposed on the second active area as a second conducting layer; carrying out work function adjustment on the first conducting layer and/or the second conducting layer; and after the work function adjustment is carried out, patterning the first conducting layer, the second conducting layer and the high-k dielectric layer, and forming a first grid electrode disposed in the first active area, a first high-k dielectric layer disposed below the first grid electrode, a second grid electrode disposed in the second active area and a second high-k dielectric layer disposed below the second grid electrode. According to the invention, the work function adjustment is carried out on the first conducting layer and/or the second conducting layer, an etching process is unnecessary, and the high-k dielectric layer is not damaged.

The invention provides a semiconductor structure. The structure comprises a substrate, a semiconductor substrate, back gate dielectric layers, back gates, cavities, a gate stack, side walls and source/drain regions, wherein the gate stack is arranged on the semiconductor substrate; the side walls are arranged on the side walls of the gate stack; the source/drain regions are embedded in the semiconductor substrate and are arranged on the two sides of the gate stack; the cavities are embedded in the substrate; the semiconductor substrate is suspended above the cavities; in the direction of the gate length, the middle thickness of the semiconductor substrate is greater than the thickness of the two sides; in the direction of the gate width, the semiconductor substrate is connected with the substrate; the back gate dielectric layers are arranged on the side walls of the semiconductor substrate; and the back gates are arranged on the side walls of the back gate dielectric layers. Correspondingly, the invention also provides a preparation method of the semiconductor structure. The semiconductor structure and the preparation method are beneficial to suppressing the short channel effect, adjusting the threshold voltage of the semiconductor device, improving the device performances, reducing the cost and simplifying the process.

The invention discloses a p-type metal oxide current barrier layer Ga2O3 vertical metal oxide semiconductor field effect transistor, which mainly solves the problem of low breakdown voltage caused by incapability of forming a pn junction in the prior art. The device comprises a drain electrode (1), a gallium oxide substrate (2), a gallium oxide drift layer (3), a gallium oxide channel layer (4), a gate dielectric layer (5) and a gate electrode (6) from bottom to top. Current blocking layers (7) are arranged on the two sides of the gallium oxide drift layer (3), a current aperture (8) is formed in the middle of the gallium oxide drift layer (3), and source electrodes (9) are arranged on the two sides of the gallium oxide channel layer (4) and the gate dielectric layer (5). The current blocking layer (7) is made of a p-type metal oxide material doped with boron element, and forms two heterojunctions with the gallium oxide drift layer (3) and the gallium oxide channel layer (4) respectively. The breakdown voltage of the device is greatly improved, and the device can be applied to high-power devices of industrial power and automobile power systems.

A method for forming a semiconductor structure comprises the following steps: providing a substrate which comprises a first region and a second region, and forming an interlayer dielectric layer with a gate opening on the substrate; a shielding layer covering the gate opening of the second region and exposing the gate opening of the first region is formed, and the shielding layer occupies the gate opening of the second region, so that in the step of forming a first work function material layer in the gate opening of the first region, the first work function material layer is formed on the shielding layer; in the process of removing the shielding layer and the first work function material layer located on the shielding layer, the removal process window of the first work function material layer in the second area is large, residues do not exist easily, the removal efficiency is high, and the yield can be improved. Besides, a removal process window of the shielding layer is large, residues do not exist easily, the second work function layer can better adjust the threshold voltage of the transistor in the second area, parasitic capacitance in the transistor in the second area is reduced, and the electrical performance of the semiconductor structure is good.

The invention provides a semiconductor structure and a formation method thereof. The formation method of the semiconductor structure includes providing a substrate; forming a projecting grid on the surface of the substrate; forming gate medium layers on the surfaces of the side walls of the grid; forming a channel layer on the surface of the grid medium layer; forming a medium layer on the surface of the substrate; forming a first through hole in the medium layer on each side of the grid, wherein a part of the medium layer is arranged between the first through hole and the channel layer; and forming back grids in the first through holes. The semiconductor structure formed by adopting the above method has a comparatively large channel length and can adjust the threshold voltage of a transistor by exerting voltage on the channel layer through the back grids.

The invention discloses a semiconductor structure, a forming method and a mask, and the method comprises the steps: providing a substrate, wherein the substrate comprises a first device region, a pseudo device region, a second device region and a third device region which are sequentially arranged along a first row, and a third device region, a second device region, a pseudo device region and a first device region which are sequentially arranged along a second row. The first device region, the pseudo device region, the second device region and the third device region in the first row are in central symmetry with the first device region, the pseudo device region, the second device region and the third device region in the second row respectively According to the embodiment of the invention, a first shielding layer exposes the first device region and the pseudo device region, and the exposed area of the first shielding layer is large, so that the process window of the first shielding layer is large, the process difficulty of forming the first shielding layer is reduced, and the overlay precision of the first shielding layer is improved.