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Buried channel transistor and forming method thereof

A technology of transistors and channels, applied in the field of buried channel transistors and their formation, to improve performance and prevent flicker noise

Active Publication Date: 2017-07-07
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The problem that the present invention solves is how to prevent the generation of the flicker noise of existing transistor

Method used

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  • Buried channel transistor and forming method thereof
  • Buried channel transistor and forming method thereof
  • Buried channel transistor and forming method thereof

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Embodiment Construction

[0030] As mentioned in the background art, the performance of transistors formed by existing technologies still needs to be improved. For example, existing transistors have 1 / f noise or flicker noise during operation, and the generation of 1 / f noise or flicker noise is related to conduction The smoothness of the channel has a great correlation, and the conductive channel formed by the existing transistor is basically a surface channel. In the manufacturing process, it is difficult to ensure the smoothness of the surface of the substrate. There will be defects, and the existence of defects will affect the transport of carriers. Therefore, when the existing transistors are working, flicker noise is likely to occur, which affects the performance of the device.

[0031] To this end, the present invention provides a buried channel transistor and a method for forming the same. By forming an inversion doped region in the well region, the carriers will flow along the gap between the in...

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Abstract

The invention discloses a buried channel transistor and a forming method thereof. The forming method comprises steps: a semiconductor substrate is provided, and a well area is formed in the semiconductor substrate; an inversion doping area is formed in the well area, the doping type in the inversion doping area is opposite to that in the well area, and the depth of the inversion doping area is smaller than that of the well area; a gate structure is formed on the surface of the semiconductor substrate above the inversion doping area, wherein the gate structure comprises a gate dielectric layer and a gate located on the gate dielectric layer, impurity ions are doped in the gate, and the doping type in the gate is the same as that in the well area; a source area and a drain area are formed inside the semiconductor substrate at two sides of the gate structure, the doping type in the source area and the drain area is opposite to the type of the impurity ions in the well area, and the depth of the source area and the drain area is smaller than that of the well area and larger than that of the inversion doping area. The transistor formed by the method of the invention can prevent generation of flicker noise and improve the device performance.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a buried channel transistor and a forming method thereof. Background technique [0002] Metal-oxide-semiconductor (MOS) transistors are the most basic devices in semiconductor manufacturing. They are widely used in various integrated circuits. According to the main carrier and the type of doping during manufacturing, they are divided into NMOS and PMOS transistors. [0003] The prior art provides a method for manufacturing a MOS transistor. Including: providing a semiconductor substrate, forming an isolation structure on the semiconductor substrate, the semiconductor substrate between the isolation structures is an active region, and forming a well region (not shown) in the active region; through the first ion implantation Doping impurity ions on the surface of the well region to adjust the threshold voltage of the subsequently formed transistor; sequentially forming a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/06H01L29/423
CPCH01L29/0684H01L29/42372H01L29/66477H01L29/7838H01L21/823412H01L21/823418H01L21/82345H10B41/42H10B41/35H01L21/26513H01L21/266H01L21/32139H01L21/76224H01L21/823807H01L21/823814H01L21/823828H01L21/823864H01L21/823878H01L27/0922H01L29/04H01L29/0649H01L29/0688H01L29/0847H01L29/1033H01L29/1083H01L29/1095H01L29/1608H01L29/161H01L29/167H01L29/66825
Inventor 邱慈云克里夫·德劳利辜良智江宇雷余达强
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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