Formation method of semiconductor device

Abstract

Disclosed is a formation method of a semiconductor device. The method comprises: providing a semiconductor substrate, and forming an isolation structure in the substrate, wherein the isolation structure isolates the substrate to a first active area and a second active area, and the types of the first active area and the second active area are opposite; forming a high-k dielectric layer and a conducting layer on the high-k dielectric layer on the substrate, defining the conducting layer disposed in the first active area as a first conducting layer, and defining the conducting layer disposed on the second active area as a second conducting layer; carrying out work function adjustment on the first conducting layer and / or the second conducting layer; and after the work function adjustment is carried out, patterning the first conducting layer, the second conducting layer and the high-k dielectric layer, and forming a first grid electrode disposed in the first active area, a first high-k dielectric layer disposed below the first grid electrode, a second grid electrode disposed in the second active area and a second high-k dielectric layer disposed below the second grid electrode. According to the invention, the work function adjustment is carried out on the first conducting layer and / or the second conducting layer, an etching process is unnecessary, and the high-k dielectric layer is not damaged.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor device. Background technique [0002] In the existing metal gate technology, the threshold voltage of the transistor can be adjusted by adjusting the work function of the transistor, thereby improving the performance of the transistor. Considering that the working principles of NMOS transistors and PMOS transistors are different, if the work function of the metal gate of the NMOS transistor is reduced and the work function of the metal gate of the PMOS transistor is increased, the threshold voltage of the NMOS transistor and the PMOS transistor can be reduced, thereby improving the performance of the transistor. For example, the work function range of the metal gate of the NMOS transistor is about 4.1-4.3 eV, and the work function range of the metal gate of the PMOS transistor is about 5.0-5.2 eV. Therefore, in the prior art, different...

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Problems solved by technology

[0009] The problem solved by the present invention is that the metal gate formed by using the prior art is applied to the transistor, resulting in poor performance of the transistor

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