Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure. The structure comprises a substrate, a semiconductor substrate, back gate dielectric layers, back gates, cavities, a gate stack, side walls and source / drain regions, wherein the gate stack is arranged on the semiconductor substrate; the side walls are arranged on the side walls of the gate stack; the source / drain regions are embedded in the semiconductor substrate and are arranged on the two sides of the gate stack; the cavities are embedded in the substrate; the semiconductor substrate is suspended above the cavities; in the direction of the gate length, the middle thickness of the semiconductor substrate is greater than the thickness of the two sides; in the direction of the gate width, the semiconductor substrate is connected with the substrate; the back gate dielectric layers are arranged on the side walls of the semiconductor substrate; and the back gates are arranged on the side walls of the back gate dielectric layers. Correspondingly, the invention also provides a preparation method of the semiconductor structure. The semiconductor structure and the preparation method are beneficial to suppressing the short channel effect, adjusting the threshold voltage of the semiconductor device, improving the device performances, reducing the cost and simplifying the process.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] In order to improve the performance and integration of integrated circuit chips, the feature size of devices has been continuously reduced according to Moore's law, and has now entered the nanometer scale. As the size of devices shrinks, power consumption and leakage current become the most concerned issues. Silicon on Insulator SOI (Silicon on Insulator) structure has become the preferred structure of deep submicron and nanoscale MOS devices because it can well suppress the short channel effect and improve the ability of devices to be scaled down. [0003] With the continuous development of SOI technology, in the prior art literature "Silicon-on-Nothing-an Innovative Process for Advanced CMOS" (IEEE Electronic Devices Transactions, Vol. 147, No. 11, 2000), Malgorzata Jurcazak, ...

AI Technical Summary

Problems solved by technology

The epitaxial SiGe sacrificial layer process increases the process steps of device manufacturing, and at the same time increases the complexity of the process; and with the reduction of device feature size, the requirement for ultra-shallow junction depth of devices also makes ion implantation a problem. There are still many challenges to be actually used in the current VLSI manufacturing process

[0006] On the other hand, threshold voltage control of semiconductor devices becomes more and more difficult as the size of semiconductors decreases, dopant fluctuations, etc.

Images