3results about How to "Improve overlay accuracy" patented technology

The application discloses a method for improving overlay accuracy, and relates to the technical field of semiconductors, and comprises the following steps: setting overlay accuracy marks in each alignment mark area of a mask layer; calculating an overlay adjustment amount corresponding to the mask layer by a wafer pre-alignment system; the overlay adjustment amount is obtained by calculating based on measurement parameters of wafer exposure; the measurement parameters comprise symmetry and asymmetry rotation parameters and expansion parameters of an exposure unit in each direction, and the overlay adjustment amount comprises false compensation calculated by a machine table due to deformation of adjacent layer exposure areas; calculating a pre-compensation amount of the mask layer based on the set overlay accuracy marks and the measurement parameters; the pre-compensation amount is used for eliminating the false compensation in the overlay adjustment amount; and calculating an overlay adjustment value of a next exposure process based on the overlay adjustment amount and the pre-compensation amount. According to the scheme, the false compensation caused by differences between front and rear layers due to exposure is subtracted from the overlay adjustment amount output by the original wafer pre-compensation system, and the overlay accuracy is improved.

The application provides a method for obtaining overlay yield in advance, comprising: performing photolithography on epitaxial layers with different thicknesses respectively; measuring the epitaxial layers after photolithography to obtain a plurality of sets of overlay deviation data; establishing a plurality of fitting functions according to the thicknesses of the epitaxial layers and the overlay deviation data; and obtaining the overlay yield of an epitaxial layer to be photolithographed according to the fitting functions and the thickness of the epitaxial layer to be photolithographed. The application performs photolithography on epitaxial layers with different thicknesses, obtains a plurality of sets of overlay deviation data, establishes fitting functions by using the overlay deviation data, and finally obtains the overlay yield of an epitaxial layer to be photolithographed by using the fitting functions, thereby improving the overlay precision of the epitaxial layer, ensuring the accuracy of overlay, and avoiding the situation that the epitaxial layer needs to be photolithographed due to overlay abnormality.

The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a first initial structure, and forming a first opening located in a first region and an alignment structure located in a second region; providing a second initial structure, wherein each of the first stacking layer and the second stacking layer comprises a first sub-layer and a second sub-layer which are alternately stacked; the side, provided with the first stacking layer, of the first initial structure and the side, provided with the second stacking layer, of the second initial structure are bonded, the first area and the third area are correspondingly bonded, and the second area and the fourth area are correspondingly bonded; removing the second substrate; forming a second opening aligned with the first opening in the second stack layer based on the alignment structure; wherein after the bonding process is executed or before the bonding process is executed, the first sub-layer and the second sub-layer which are alternately stacked on the fourth area in the second stacking layer are replaced with the filling layer, and the light transmittance of the filling layer is larger than that of the second stacking layer.