10results about How to "Improve overlay accuracy" patented technology

The invention provides an environment control assembly, photoetching equipment and a manufacturing method of a gas turning channel, the environment control assembly comprises a gas supply channel and a gas turning channel which are communicated, the gas turning channel is gradually narrowed in the direction away from the gas supply channel and forms a gas outlet, and the gas supply channel is communicated with the gas turning channel. The gas supply channel is used for blowing clean gas to the side wall of the gas turning channel, after the clean gas is sprayed out of the gas outlet, one part of the clean gas forms a first gas flow area, and the other part of the clean gas is mixed with external gas to form vortex so as to prevent the external gas from entering the first gas flow area. According to the configuration, the air pressure of the first airflow area is larger than that of the external area, external air is blocked outside the first airflow area, meanwhile, overflowing clean air and the external air form vortex through the air turning channel, and the blocking effect of the first airflow area is further improved.

The application discloses a method for improving overlay accuracy, and relates to the technical field of semiconductors, and comprises the following steps: setting overlay accuracy marks in each alignment mark area of a mask layer; calculating an overlay adjustment amount corresponding to the mask layer by a wafer pre-alignment system; the overlay adjustment amount is obtained by calculating based on measurement parameters of wafer exposure; the measurement parameters comprise symmetry and asymmetry rotation parameters and expansion parameters of an exposure unit in each direction, and the overlay adjustment amount comprises false compensation calculated by a machine table due to deformation of adjacent layer exposure areas; calculating a pre-compensation amount of the mask layer based on the set overlay accuracy marks and the measurement parameters; the pre-compensation amount is used for eliminating the false compensation in the overlay adjustment amount; and calculating an overlay adjustment value of a next exposure process based on the overlay adjustment amount and the pre-compensation amount. According to the scheme, the false compensation caused by differences between front and rear layers due to exposure is subtracted from the overlay adjustment amount output by the original wafer pre-compensation system, and the overlay accuracy is improved.

The invention provides a preparation method of a semiconductor device, and the preparation method comprises the steps: after removing a patterned first photoresist layer used for carrying out the ion implantation of a gate structure, cleaning a semiconductor structure through employing an acid pickling process and an alkali cleaning process, so as to remove a natural oxidation layer on the surface of the semiconductor structure, according to the invention, the back surface of the semiconductor structure is cleaned by using the deionized water, so that the back dielectric layer on the back surface of the substrate can be prevented from being in contact with the hydrofluoric acid solution; therefore, the condition that the current-layer wafer forms more exposure dead pixels in the following photoetching process is avoided, the overlay precision of subsequent metal zero-layer through hole etching is improved, the yield and reliability of the device are improved, and meanwhile, the condition that the back dielectric layer on the back surface of the substrate is stripped and then falls off to pollute and / or smash the front surface of the lower-layer wafer is also avoided.

The application provides a method for obtaining overlay yield in advance, comprising: performing photolithography on epitaxial layers with different thicknesses respectively; measuring the epitaxial layers after photolithography to obtain a plurality of sets of overlay deviation data; establishing a plurality of fitting functions according to the thicknesses of the epitaxial layers and the overlay deviation data; and obtaining the overlay yield of an epitaxial layer to be photolithographed according to the fitting functions and the thickness of the epitaxial layer to be photolithographed. The application performs photolithography on epitaxial layers with different thicknesses, obtains a plurality of sets of overlay deviation data, establishes fitting functions by using the overlay deviation data, and finally obtains the overlay yield of an epitaxial layer to be photolithographed by using the fitting functions, thereby improving the overlay precision of the epitaxial layer, ensuring the accuracy of overlay, and avoiding the situation that the epitaxial layer needs to be photolithographed due to overlay abnormality.

The application provides a thick film overlay accuracy measurement method, which comprises the following steps: providing a wafer with a prepared front layer overlay mark; preparing a mask which only opens the overlay mark between the current layer and the front layer according to the overlay mark coordinates between the current layer and the front layer; obtaining a plurality of grooves with different depths for exposing the overlay mark of the front layer through photoetching and etching; the depths are respectively represented as H1, H2,..., and Hn; the grooves expose the upper surface of the overlay mark of the front layer through their bottoms; spinning a photoresist layer on the wafer to cover the grooves with different depths; transferring the overlay mark of the current layer to the photoresist layer by using the mask; respectively measuring the overlay accuracy of the overlay mark of the current layer relative to the overlay mark of the front layer in the grooves with different depths to obtain the first, second,..., and nth overlay accuracy values corresponding to H1, H2,..., and Hn; and preparing a relationship curve of H1, H2,..., and Hn and the first, second,..., and nth overlay accuracy values. The method can optimize measurement and find the optimal solution of the etching depth corresponding to the overlay accuracy.

The invention discloses a real-time heat dissipation chuck device and a heat dissipation control method. The chuck device comprises a cover plate, a flow channel component and a heat pipe component which are sequentially arranged in a stacked mode. A silicon wafer is placed in the center of the runner component, an annular runner is arranged around the silicon wafer, and a cover plate covers the annular runner; a heat pipe component is arranged below the flow channel component and comprises a heat pipe array, the heat pipe array extends to the position below the annular flow channel in the row direction, and the effective heat transfer area of the heat pipe array covers the exposure area of the upper surface of the silicon wafer. The method is beneficial to improving the stability and uniformity of the global temperature of the silicon wafer under the exposure working condition, and is beneficial to reducing the thermal deformation of the silicon wafer so as to improve the alignment precision.

The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure, and the preparation method comprises the steps: providing a first initial structure, and forming a first opening located in a first region and an alignment structure located in a second region; providing a second initial structure, wherein each of the first stacking layer and the second stacking layer comprises a first sub-layer and a second sub-layer which are alternately stacked; the side, provided with the first stacking layer, of the first initial structure and the side, provided with the second stacking layer, of the second initial structure are bonded, the first area and the third area are correspondingly bonded, and the second area and the fourth area are correspondingly bonded; removing the second substrate; forming a second opening aligned with the first opening in the second stack layer based on the alignment structure; wherein after the bonding process is executed or before the bonding process is executed, the first sub-layer and the second sub-layer which are alternately stacked on the fourth area in the second stacking layer are replaced with the filling layer, and the light transmittance of the filling layer is larger than that of the second stacking layer.

Embodiments of the present disclosure relate to a multiple patterning method, an electronic device, and a computer-readable storage medium. The method includes: exposing a first mask and a second mask for forming a via layer to form a photolithographic via pattern, wherein at least the first mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a first direction according to a minimum design rule, and the second mask is alternately provided with a light-transmitting portion and a non-light-transmitting portion extending along a second direction perpendicular to the first direction; transferring the photolithographic via pattern to a corresponding first hard mask by etching to form a first via portion; etching the second hard mask under the first hard mask through a third mask so that the first via portion corresponding to the via layer in the layout among the multiple first via portions extends to the second hard mask to form a via; forming a wiring layer based on the layout of the wiring layer, and the layouts of the wiring layer and the via layer are designed based on the minimum design rule. The technology disclosed in the present disclosure can achieve a larger process window and higher overlay accuracy.

The present application relates to an alignment pattern, a semiconductor device, an electronic device and an exposure compensation method. The alignment pattern is located in a cutting path; the alignment pattern includes a first-layer alignment pattern and at least one measurement alignment pattern; the first-layer alignment pattern is located on the first-layer semiconductor film layer, including a central symmetric pattern with a common center point and axis of symmetry, and a rhombus located within the central symmetric pattern; at least one measurement alignment pattern is located on different semiconductor film layers stacked in sequence in a direction away from the first-layer semiconductor film layer; at least one measurement alignment pattern is a rhombus; the offset vector of at least one measurement alignment pattern compared to the first-layer alignment pattern is used to indicate the overlay offset of the semiconductor film layer. The present application can perform real-time measurement and timely compensation of the overlay offset in the chip manufacturing stage, thereby improving the overlay accuracy of the chip and thus improving the yield of the lithography product.

The present invention provides a method for monitoring the annealing temperature of a laser annealing machine, forming a zero mark layer pattern on a wafer to be tested; performing ion implantation and laser annealing processes on the surface of the wafer to be tested; measuring the resistance of the wafer to be tested in the Z direction to obtain a resistance measurement value; forming an overlay layer pattern on the wafer to be tested; measuring the overlay accuracy between the zero mark layer pattern and the overlay layer pattern to obtain an X-direction value and a Y-direction value; adjusting the annealing temperature of the laser annealing machine according to the measured X-direction value, Y-direction value and resistance measurement value. The present invention realizes the monitoring of the laser annealing machine in three dimensions, can predict in advance the influence of the laser annealing temperature fluctuation within the chip on the overlay accuracy of the subsequent process photolithography layer, and then timely adjusts the uniformity of the laser annealing temperature, improves the overlay accuracy of the product, and improves the product yield.