MOSFET (metal oxide semiconductor field effect transistor) and manufacturing method thereof

Abstract

The invention provides an MOSFET (metal oxide semiconductor field effect transistor) and a manufacturing method thereof. The MOSFET comprises a semiconductor substrate, a first insulating buried layer on the semiconductor layer, a back gate formed in a semiconductor layer on the first insulating buried layer, a second insulating buried layer on the first semiconductor layer, source / drain areas formed in a second semiconductor layer on the second insulating buried layer, a gate on the second semiconductor layer, and electric connection for the source / drain areas, the gate and the back gate. The back gate is located in one of the source / drain areas and below a groove area and not located below the other one of the source / drain areas. The electric connection includes a common conductive channel of the back gate and the source / drain areas. The short-channel channel inhibition effect is improved by the aid of the asymmetrical back gate of the MOSFET, and the area of a chip is reduced by the common conductive channel.

Description

technical field [0001] The present invention relates to a MOSFET and a manufacturing method thereof, more particularly, to a MOSFET with a back gate and a manufacturing method thereof. Background technique [0002] An important development direction of integrated circuit technology is to scale down the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) to improve integration and reduce manufacturing costs. However, it is well known that short-channel effects occur as the size of MOSFETs decreases. As the size of the MOSFET is scaled down, the effective length of the gate is reduced, so that the proportion of depletion layer charge that is actually controlled by the gate voltage is reduced, so that the threshold voltage decreases as the channel length decreases. [0003] Yan et al. proposed in "Scaling the Si MOSFET: From bulk to SOI to bulk" (IEEE Trans. Elect. Dev., Vol. 39, p. 1704, July 1992), in SOI MOSFET, by A ground plane (that is, a grounded back ...

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Problems solved by technology

[0004] However, the above-mentioned SOI MOSFET with a back gate must be grounded or biased at a predetermined potential during operation, thus requiring additional chip area for providing an electrical contact to the back gate, for example for forming additional channels and wiring

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