7 results about "Borophosphosilicate glass" patented technology

An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

The application provides a semiconductor structure, a preparation method and device of the semiconductor structure, relates to the technical field of semiconductors, and aims to solve the technical problem of high preparation cost of the semiconductor structure. The preparation method comprises the following steps: providing a substrate, wherein a groove is formed in the substrate; providing a silicon-oxygen polymer solution on the surface of the substrate, and forming a silicon-oxygen polymer layer by spin coating the silicon-oxygen polymer solution through a spin-on dielectric process, wherein the silicon-oxygen polymer solution contains a doping element, and the doping element comprises boron and phosphorus; and performing heat treatment on the silicon-oxygen polymer layer, wherein the temperature threshold of the heat treatment is 120-150 DEG C. The silicon-oxygen polymer layer is irradiated with ultrasonic waves for a preset time length, so as to form a porous silicon layer containing silicon hydroxide bonds; and an oxidizing gas is provided to the porous silicon layer, the oxidizing gas reacts with the silicon hydroxide bonds in the porous silicon layer, so as to form a borophosphosilicate glass film; and the borophosphosilicate glass film fills the groove. The application can reduce the preparation cost of the semiconductor structure.

Support (200) comprising: a support body (202); a bonding material (204) on a first main surface (208) of the support body (202), wherein the support (200) is configured to be attached to a semiconductor wafer via the bonding material (204) by wafer bonding, wherein the support body (202) contains one or more of silicon, boron phosphosilicate glass, borosilicate glass, phosphosilicate glass, boron nitride, polycrystalline silicon, silicon carbide; and dopants integrated in a first part (216) of the support (200) on the first main surface (208), wherein the dopants are configured to eject from the support (200) by thermal processing and are configured to form an n-type or p-type doping in the semiconductor wafer.

The present invention provides a method for controlling the height of a semiconductor dummy component, comprising the following steps: (1) cutting 2 to 5 mutually parallel grooves on the front side of the semiconductor dummy component and cutting 2 to 5 mutually parallel grooves on the back side of the semiconductor dummy component, the difference between the number of grooves on the front side and the back side is 1, the grooves on the front side and the grooves on the back side are parallel to each other, and the distances between adjacent projections of the grooves on the front side of the semiconductor dummy component and the grooves on the back side of the semiconductor dummy component on the plane are equal and do not overlap; (2) depositing a stress release layer on the bottom surface and the side surface of the groove of the semiconductor dummy component, the material of the stress release layer is borosilicate glass or borophosphosilicate glass; (3) performing annealing at 60 to 120° C. The method of the present invention greatly reduces the height of the semiconductor dummy component by limiting the number of grooves and the cutting position, and reduces the shadow caused to the normal component by the semiconductor dummy component during the process of laying the semiconductor component.

The invention provides an IGBT (Insulated Gate Bipolar Translator) device preparation method and an IGBT device. The preparation method comprises the following steps of providing a substrate; forming a plurality of gate trenches on the substrate; forming a first insulating layer with a preset thickness in the gate trench; oxidizing the side wall of the n-type emitter layer, etching the substrate and forming an undercut structure at the opening of the gate trench; etching the first nitride layer and the first insulating layer in the gate trench until the thickness of the first insulating layer reaches a set threshold value; growing gate oxide layers on the side walls of the plurality of gate trenches and the surface of the substrate; the polycrystalline silicon gates are formed by filling polycrystalline silicon in the plurality of gate trenches, and the height of the polycrystalline silicon gates is smaller than the depth of the gate trenches; depositing an interlayer dielectric layer on the plurality of gate trenches and exposing the surface of the substrate, wherein the interlayer dielectric layer is a boron-phosphorosilicate glass layer; forming a plurality of contact holes in the surface of the substrate through self-alignment etching, wherein the contact holes extend to the p-type well region layer; and filling the plurality of contact holes to form contact hole filling, and forming a front metal layer on the first surface of the substrate.

The invention relates to a preparation method of a semiconductor device. According to the method, the patterned oxide layer comprising the silicon dioxide layer and the boron phosphosilicate glass layer is subjected to reflux treatment, so that the corner at the position of the contact hole becomes smooth, the geometric obstacle of metal layer deposition is eliminated, and a foundation is laid for uniform deposition of the metal layer. Meanwhile, reverse sputtering and circular treatment of the primary metal layer are adopted, uniform deposition of the metal layer along the hole wall is promoted, the problem that holes and gaps exist in the metal layer due to the fact that the contact hole with the high aspect ratio is sealed in advance is effectively solved, and then the thickness uniformity of the metal layer is effectively improved.

The present invention discloses a method for planarizing a micro-system thin film. The method for planarizing the micro-system thin film includes: depositing a borophosphosilicate glass layer on a patterned thin film; then, performing rapid thermal annealing and annealing treatment on the borophosphosilicate glass layer; finally, polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness. Through the annealing treatment, the borophosphosilicate glass can effectively flow back, reducing the step difference; at the same time, the doped boron (B) and phosphorus (P) can be repaired at different interfaces to form a uniform concentration; when performing the polishing treatment, due to the higher stability and smaller step difference of the sacrificial layer, the polishing speed can be increased and the polishing amount can be reduced, effectively controlling the thickness, flatness and stability of the sacrificial layer thin film; at the same time, a large amount of CMP consumables such as polishing pads, polishing liquids, trimmers, etc. can be saved, and the output is higher, and the economic benefits are very obvious.