55 results about "Borophosphosilicate glass" patented technology

CMOS devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant through openings in a masking layer and through channel regions of the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) diffusion source within the insulation layer underlying the gate regions of the SOI wafer substantially between the source and drain. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the p- and n-wells, thereby forming asymmetric retrograde dopant profiles in the channel under the gate. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

FinFET devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and methods for producing the same. The methods involve dopant implants into the insulator layer, thereby creating borophosphosilicate glass (BPSG) diffusion sources within the insulation layer underlying the active regions of the SOI wafer. Backend high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the active regions, thereby forming a retrograde dopant profile extending towards the channel region. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

A semiconductor substrate having an SOI layer is provided. Between an SOI layer and a glass substrate, a bonding layer is provided which is formed of one layer or a plurality of layers of phosphosilicate glass, borosilicate glass, and/or borophosphosilicate glass, using organosilane as one material by a thermal CVD method at a temperature of 500° C. to 800° C.

A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).

A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480 DEG C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750 DEG C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.1 to 2.0 wt % fluorine.

A deposition method includes forming a nucleation layer over a substrate, forming a layer of a first substance at least one monolayer thick chemisorbed on the nucleation layer, and forming a layer of a second substance at least one monolayer thick chemisorbed on the first substance. The chemisorption product of the first and second substance may include silicon and nitrogen. The nucleation layer may comprise silicon nitride. Further, a deposition method may include forming a first part of a nucleation layer on a first surface of a substrate and forming a second part of a nucleation layer on a second surface of the substrate. A deposition layer may be formed on the first and second parts of the nucleation layer substantially non-selectively on the first part of the nucleation layer compared to the second part. The first surface may be a surface of a borophosphosilicate glass layer. The second surface may be a surface of a rugged polysilicon layer. The first and second part of the nucleation layer may be formed simultaneously.

To provide an electro-optical device, which has a high manufacturing yield and high quality display, the electro-optical device includes above a substrate, display electrodes, at least one of wiring lines and electronic elements that drive the display electrodes, and interlayer insulating films provided below the display electrodes to electrically insulate the display electrodes and at least one of the wiring lines and electronic elements from each other. At least one of the interlayer insulating films includes a boron phosphorus silicate glass film and has its top face subjected to planarizing treatment by being put into a fluidized state.

A method and apparatus for controlling dopant concentration during borophosphosilicate glass film deposition on a semiconductor wafer to reduce consumption of nitride on the semiconductor wafer. In one embodiment of the invention, the method starts by placing a substrate having a nitride layer in a reaction chamber and providing a silicon source, an oxygen source and a boron source into the reaction chamber while delaying providing a phosphorous source into the reaction chamber to form a borosilicate glass layer over the nitride layer. The method continues by providing the silicon, oxygen, boron and phosphorous sources into the reaction chamber to form a borophosphosilicate film over the borosilicate glass layer.

An inkjet printer includes: an inkjet printhead having an exposed corrodible structure containing silicon nitride, borophosphosilicate glass (BPSG) or silicon oxide; and an ink reservoir containing said ink which is in fluid communication with said printhead. The ink includes: water; a dye; and a metal additive for minimizing corrosion of the exposed structure.

The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O₃. When done at temperatures higher than approximately 480 degrees C., the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

A method of forming a semiconductor device, the method including the following processes. A groove is formed in a semiconductor substrate. A gate electrode is formed in the groove. A boron-phosphorus silicate glass film is formed over the gate electrode. An etching process is performed using the boron-phosphorus silicate glass film as an etching stopper for preventing the gate electrode from being removed.

The invention discloses a method for manufacturing a double-sided PERC high-efficiency crystalline silicon solar cell. The method comprises the following steps of (1) texturing, (2) diffusion including crystalline silicon diffusion, (3) laser doping including the laser doping of a diffused crystalline silicon, (4) etching including the removal of diffused borophosphosilicate glass, (5) back passivation including the production of a SiO2-Al2O3-SiNx:H laminated passivation film with a thickness of 80-100 nm, (6) front side film coating including the generation of a SiO2-SiNx anti-reflection filmwith thickness of 80-90 nm by using the PECVD technology, (7) Backside laser doping and trenching including the formation of a corresponding P++ layer, wherein the line width of each of 120 laser doped region sub-gate lines is 40-45 micrometers, and composite 1.6 mm main grids are set, and (8) backside printing including the formation of a back aluminum grid pattern, the collection of current andsintering to form the double-sided PERC high-efficiency crystalline silicon solar energy battery.

A method for forming a microfluidic channel with improved flow characteristics for one or more analytes is disclosed. A microfluidic channel having modified surfaces is formed in a glass layer or glass substrate. The glass surfaces of the microfluidic channel are modified by the addition of a layer of borophosphosilicate glass. The addition of the borophosphosilicate glass results in an improved flow velocity profile of the analyte. As a result, control over the position and movement of analytes within the solution is improved.

An inkjet printer includes: an inkjet printhead having an exposed corrodible structure containing silicon nitride, borophosphosilicate glass (BPSG) or silicon oxide; and an ink reservoir containing said ink which is in fluid communication with said printhead. The ink includes: water; a dye; and a metal additive for minimizing corrosion of the exposed structure.