SOI CMOS device with reduced DIBL

Abstract

CMOS devices formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant through openings in a masking layer and through channel regions of the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) diffusion source within the insulation layer underlying the gate regions of the SOI wafer substantially between the source and drain. Backend, high temperature processing steps induce diffusion of the dopants contained in the diffusion source into the p- and n-wells, thereby forming asymmetric retrograde dopant profiles in the channel under the gate. The method can be selectively applied to selected portions of a wafer to tailor device characteristics, such as for memory cells.

Description

RELATED APPLICATIONS

[0001] This application is a continuation of U.S. application Ser. No. 10 / 801993 filed Mar. 16, 2004 which issued (issue date unknown) as U.S. patent (patent number unknown).BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention relates to the field of semiconductor devices and fabrication processes and, in particular, to CMOS devices formed in a silicon-on-insulator (SOI) technology with improved avoidance of short channel effects, such as reduced drain induced barrier lowering (DIBL) and a method for fabricating the same, including arrays of memory cells with peripheral logic circuits.

[0004] 2. Description of the Related Art

[0005] There is an ever-present desire in the semiconductor fabrication industry to achieve individual devices with smaller physical dimensions. Reducing the dimensions of devices is referred to as scaling. Scaling is desirable in order to increase the number of individual devices that can be placed on a given a...

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