10results about How to "High density integration" patented technology

The invention provides a nanoelectrode preparation method of a two-dimensional material memristor, and relates to the technical field of semiconductor device preparation, and the method comprises the steps: carrying out the spin coating of a PMMA diluent on a substrate, carrying out the electron beam exposure, carrying out the low-temperature development, and forming a patterned bottom contact electrode; performing physical vapor deposition, photoresist removal and stripping on the patterned bottom contact electrode to obtain a bottom contact electrode; preparing an insulating layer on the substrate for preparing the bottom contact electrode by using an atomic layer deposition mode; copper substrate etching is carried out on the two-dimensional material with the copper substrate, and the two-dimensional material with the copper substrate is transferred to the position above the insulating layer; performing patterning treatment on the transferred two-dimensional material to obtain a patterned two-dimensional material electrode; pMMA diluent is spin-coated on the surface of the substrate after patterning of the two-dimensional material, electron beam exposure and low-temperature development are carried out after baking and glue solidification, and a patterned top contact electrode is formed; and performing physical vapor deposition on the patterned top contact electrode to obtain the top contact electrode. The size of the device can be greatly reduced, and the performance uniformity of the device is improved.

The invention discloses a volatile threshold switching device based on an atomic-scale geometric confinement layer and a preparation method thereof. The device comprises a substrate layer, a bottom electrode layer, a functional active layer, a geometric confinement layer and a top electrode layer which are stacked in sequence, the functional active layer is used for providing active metal ions to form conductive filaments; the functional active layer is made of a two-dimensional layered ferroelectric material; the geometric confinement layer is made of hexagonal boron nitride sheets, and the thickness range of the hexagonal boron nitride sheets is 1-5 hexagonal boron nitride atomic layers. According to the invention, the h-BN material with atomic-scale lattice defects is introduced as the geometric confinement layer, and the diameter of the conductive filament formed by copper ions in the functional active layer is physically limited by using the atomic-scale ion sieve effect of the h-BN material, so that the problem of failure caused by overgrowth of the filament in a traditional device is solved.

This utility model relates to the field of hydrogen energy technology, and in particular to an integrated multi-functional high-pressure hydrogen cylinder valve. It includes a main control solenoid valve, a manual valve, an overflow valve, a venting valve, and a temperature-driven venting device mounted on the valve body. All of these components are located on the side of the valve body. This utility model employs an internal channel layout, integrating multiple modules such as the main control solenoid valve, manual valve, overflow valve, and temperature-driven venting device. This significantly simplifies the pipeline structure, reduces leakage risk, and achieves a revolutionary structure characterized by high-density integration, ultra-thin flatness, and high reliability maintenance.

The application provides a compact high-speed modulator, which comprises an input waveguide, a light splitting structure for splitting light input by the input waveguide into a first light path and a second light path, a first photonic crystal region for modulating the first light path by thermal light, and a second photonic crystal region for modulating the first light path by electro-optic modulation, a third photonic crystal region for modulating the second light path by electro-optic modulation, and a light combining structure for combining the modulated first light path and the second light path and outputting the combined light path through an output waveguide, wherein the first to third photonic crystal regions each comprise a plurality of periodically arranged structure units, each structure unit comprises a one-dimensional topological lattice waveguide and a first multi-lattice expansion region and a second multi-lattice expansion region located on two sides of the one-dimensional topological lattice waveguide respectively, and by modulating the phase shift and the coupling strength at the interface, topological boundary states with different characteristics are excited in the band gap.

The invention provides a package substrate structure and a preparation method thereof. The preparation method comprises the following steps: respectively arranging pattern conductive layers on the upper surface and the lower surface of a core plate layer, arranging a medium adding layer on the pattern conductive layers, arranging a silicon-based middle adding layer on the medium adding layer, and arranging patterned solder mask layers on the upper surface and the lower surface of the formed structure to lead out conductive connection. The silicon-based middle layer is arranged on the medium adding layer of the packaging substrate, the warping problem of the packaging substrate is reduced by utilizing the high flatness and low ductility of the silicon-based middle layer on the medium adding layer, and the plate surface flatness of the packaging substrate is improved; meanwhile, the dielectric constant and the dielectric loss factor of the silicon-based intermediate layer are relatively low, so that the performance of the packaging substrate can be improved; in addition, through the characteristic that a finer circuit can be manufactured through the silicon-based middle layer, a packaging substrate structure integrated with higher density is achieved. And finally, the performance of the packaging substrate is further improved by wrapping the middle conductive layer with the two silicon-based middle layers.

This application relates to the field of in-memory computing memory technology, and more particularly to a three-dimensional ferroelectric memory with an IGZO channel and its fabrication method. The three-dimensional ferroelectric memory with an IGZO channel includes: a bottom global gate line; a center select gate extending vertically relative to the bottom global gate line; a semiconductor stack structure including a gate metal layer, a ferroelectric layer, a gate oxide layer, and an IGZO channel sequentially surrounding the center select gate; a drain and a source extending horizontally relative to the center select gate into the semiconductor stack structure and contacting the ferroelectric layer; and multiple pairs of drains and sources spaced apart along the extension direction of the center select gate to form multiple ferroelectric memory transistor cells. The three-dimensional ferroelectric memory with an IGZO channel of this application improves the durability and reliability of non-volatile memory devices.

This application relates to the field of flexible electronics technology, and more particularly to multilayer flexible electronic devices, their fabrication methods, and applications. The fabrication method includes: providing a film unit, comprising a flexible film and a circuit bonded to a surface of the flexible film, wherein the surface of the film unit with the circuit bonded is designated as a first surface, and the surface opposite to the first surface is designated as a second surface; immersing the film unit and a first substrate in a liquid, performing a first bonding treatment on the first surface and the surface of the first substrate, and removing the film unit from the liquid to obtain a film composite unit; using the first surface of the film unit that has not undergone the first bonding treatment as a front surface, and the second surface of the film composite unit as a rear surface, performing a second bonding treatment on the front and rear surfaces; peeling the first substrate in the film composite unit after the second bonding treatment, so that the first surface in the film composite unit forms a new front surface; repeating the second bonding treatment and peeling treatment steps to obtain a multilayer flexible electronic device.

The application discloses a manufacturing method of a ceramic micro-flow channel carrier for high-power devices and relates to the field of ceramics. The manufacturing method comprises the following steps: after punching a green ceramic sheet, tungsten slurry is used to fill the holes and conductor patterns are printed on the surface of the green ceramic sheet; then, a bottom plate micro-flow channel layer is laminated and a sacrificial material is filled in the micro-flow channel cavities; then, the bonding interface between the cover plate and the bottom plate is subjected to ultraviolet laser roughening treatment; then, two-step isostatic pressing forming treatment is performed; after cutting into a bar, the bar is subjected to glue removal, sintering, hot pressing leveling, grinding, polishing and seed layer deposition; then, exposure development is performed and the line layer is thickened by electroplating; then, secondary photolithography processing is performed on the chip eutectic area to open a window; finally, gold tin evaporation treatment, stripping of the photoresist and cutting are performed, so that the ceramic micro-flow channel carrier for high-power devices is obtained. According to the specific manufacturing process, the mechanical strength, the dielectric property, the heat fatigue resistance and the micro-flow channel pressure resistance are improved while the heat dissipation property is maintained.

The application belongs to the technical field of optical electric field sensing, and discloses a U-shaped cascade waveguide nested micro-ring resonant cavity type electric field sensor and a preparation method thereof. The electric field sensor comprises an input coupling unit, an optical sensitive unit and a spectrum detection output interface. The optical sensitive unit comprises an incident grating, a U-shaped cascade waveguide structure, a nested micro-ring resonant cavity and an electro-optic polymer film. The nested micro-ring resonant cavity comprises a reference resonant cavity and a sensing resonant cavity. The electro-optic polymer film covers the cladding layer of the sensing resonant cavity. The application expands the equivalent free spectral range of a single resonant unit through a U-shaped feedback structure, utilizes the free spectral range difference between the two resonant units to form a vernier effect to amplify the sensing response, and simultaneously adopts a heterogeneous integrated vertical coupling mode to improve the system integration and packaging consistency, and improves the sensing sensitivity and measurement range.

The present invention discloses a method for optimizing disordered ultra-uniform solid devices based on morphology modification, which adjusts the geometric morphology of disordered ultra-uniform solids through curve functions or surface functions, thereby optimizing the photonic band gap and optical loss characteristics of disordered ultra-uniform solid devices. First, several points on the boundary between the hole and the grid wall in the disordered ultra-uniform solid are selected; second, the selected points are connected and smoothed using the curve function or the surface function; finally, the boundary of the original disordered ultra-uniform solid is replaced by the smoothed curve to complete the adjustment of its geometric morphology.