103results about How to "High density integration" patented technology

Within one pixel element 200, two display circuits corresponding to the analog display mode and the digital display mode are disposed such that they are adjacent to each other. One of these two display circuits can be selected through the circuit selection circuits 40 or 43. Since the high voltage power line 150 of the retaining circuit 110, which is used under the digital display mode, also performs as the signal selection line 88, it is possible to have the high density integration of the pixel element 200. Also, the bias voltage Vsc supplied through the selection storage capacitor line 81 is same as the signal A. Therefore, the storage capacitor line 81 is connected to the drain of the TFT 122 of the signal selection circuit 120 so that the signal line 82 for supplying the signal A can be omitted. Thus, the high-density integration of the pixel element 200 can be achieved.

The invention relates to a millimeter wave tile-type phased-array antenna TR module, and the invention aims at providing a TR module realization scheme with advantages of high reliability, low cost and high density integration for a millimeter wave frequency range high-power active phased-array antenna (APAA). The millimeter wave tile-type phased-array antenna TR module can be realized by the following scheme: a radio-frequency signal is fed from a radio-frequency vertical interconnection interface of a common port of the lower cavity bottom of the TR module, after the radio-frequency signal is performed the power distribution through a power divider mounting on the surface of a multi-layer circuit board and the like, the radio-frequency signal is fed in a multichannel amplitude-phase control chip connected with every transmit-receive channel, after the radio-frequency signal is performed the second power distribution by the multichannel amplitude-phase control chip, the amplitude-phase information of each channel radio-frequency signal is adjusted according to the state of the external control code and is outputted to a TR multi-function chip, the signal is amplified and outputted to the final power amplifier until saturation, the signal is outputted to a power switch, the emission access is gated, and the signal is transmitted to antenna radio-frequency vertical interconnection interfaces arranged on two ends of the cavity on the TR module; when the TR module receives a work, the radio-frequency signal passes through the TR module in a reverse direction.

A high density integrated optical chip. The optical chip features an optical function connected to a low minimum bending radius dielectric waveguide, and a large mode field size dielectric waveguide to interface with an external optical device, such as an optical fiber. The large mode field size dielectric waveguide is optically connected to the low minimum bending radius dielectric waveguide on the optical chip.

A non-volatile memory device includes a selection transistor coupled to a bit line. The device also includes a plurality of memory cells serially coupled to the selection transistor and at least one dummy cell located between the plurality of memory cells. The dummy cell is turned off during a programming operation of a memory cell located between the dummy cell and the selection transistor.

The present invention provides a power module and a manufacturing method thereof. The power module includes a carrier board and a lead component stacked relative to the carrier board. The lead component includes an initial plane, plural first pins and plural second pin. The initial plane includes a vertical projection overlapping with the carrier board. The first pins are electrically connected to the carrier board and vertical to the initial plane. The second pins are electrically connected to the carrier board and vertical to the initial plane. An isolation gap is disposed in the initial plane and located between the first pins and the second pins. The initial plane is separated into a first plane and a second plane by the isolation gap, so as to electrically isolate the first pins and the second pins from each other.

The invention discloses a pyroelectric infrared detector provided with a planarized heat-insulated structure and a preparation method thereof. The pyroelectric infrared detector comprises a substrate and the heat-insulated structure, wherein the heat-insulated structure is as follows: a deep notch of a corresponding figure of a lower electrode of a detector is etched on the silicon or sapphire substrate; a porous silicon dioxide layer is deposited inside the deep notch; and silicon dioxide layers or silicon nitride layers are deposited on the porous silicon dioxide layer and the substrate. The detector is easy to be integrated with other devices by means of single scale intergration, is favorable for high-density integration of detector units, has simple manufacturing technique and low processing cost, simultaneously greatly reduces the vertical height difference of steps of a mesa device structure, is easy to interconnect metals, reduces the difficulty of the processing technique of devices and the surface leakage current of the devices, improves the performance and the finished product rate of the pyroelectric infrared detector, and obviously improves the reliability of the devices. The detector provided with the structure is suitable for infrared-ultraviolet dual-range single scale intergration and manufacture of the infrared detector and a CMOS ROIC one chip integrated focal plane device.

The invention discloses a jet-printing head based on a double-carbon nanotube microbubble generator and a preparation method thereof. The jet-printing head comprises a carbon nanotube microbubble generator and a microfluid structure comprising a main channel, a capillary channel, a microcavity and a nozzle. The carbon nanotube microbubble generator and the microfluid structure are manufactured independently. A jet-printing head structure is prepared by adopting the silicon surfacing and bulk silicon processing technologies, wherein the silicon surfacing technology mainly comprises steps of manufacturing figures by photoetching, manufacturing a masking film by a magnetron sputtering technology, etching the masking film by wet process, and the like; and the bulk silicon processing technology mainly comprises the step of manufacturing the microfluid structure by combining the wet etching and dry etching. The double-carbon nanotube microbubble generator and the microfluid structure are jointed by an ultraviolet curing bonding method to form the whole jet-printing head structure. The invention has very high spatial resolution and frequency response and very low power consumption, eliminates the problem of secondary droplets, effectively enhances the quality of jet-printing figures, and has favorable superintegration potential, thereby having side application prospect in the advanced manufacturing field.

Provided are a photonic-crystal plate that forms an optical waveguide and an optical device assembly using the same, and more particularly, a vertical-type photonic-crystal plate and an optical device assembly configured to be easily integrated with surface-emitting light source devices and surface-receiving light detector devices. The photonic-crystal plate includes a plurality of cylindrical through holes formed in a thickness direction and arranged in a periodic crystal lattice structure. The plate further includes: a main crystal lattice defect that forms a main optical waveguide for passing lights in a direction perpendicular to the photonic-crystal plate; and a sub-crystal lattice defect that forms a sub-optical waveguide for causing light in a specific wavelength band among the lights passing through the main optical waveguide to be optically coupled and passing the coupled light in the direction perpendicular to the photonic-crystal plate.

The invention discloses a method for manufacturing a three-dimensional flexible stacked encapsulating structure of an embedded ultrathin chip. The method comprises choosing a flexible substrate with a single-layer metal layer, etching the single-layer metal layer on the flexible substrate to form a plurality of metal electrodes, conducting laser grooving on one side of the flexible substrate without the single-layer metal layer to form a plurality of grooves, conducting flipped thermocompression bonding with a plurality of chips on one side of the flexible substrate, provided with the plurality of grooves, thermally compressing the side of the flexible substrate, provided with the plurality of chips through thermocompression bonding and a flexible medium layer to embed the plurality of chips into the flexible medium layer, thinning one side of flexible medium layer embedded with the plurality of chips of the flexible substrate to obtain a thinned flexible medium module embedded with the plurality of chips, bending a part of the flexible medium module without the chips to stack the chips, encapsulating and curing a three-dimensional flexible encapsulating module with the plurality of stacked chips, and routing or reballing the encapsulated three-dimensional flexible encapsulating module.

Short channel effects are effectively suppressed by steep impurity concentration gradients which can be placed with improved accuracy of location and geometry while relaxing process tolerances by implanting impurities in a polysilicon seed adjacent a conduction channel of a transistor and diffusing impurities therefrom into the conduction channel. The polysilicon seed also allows the epitaxial growth of polysilicon source/drain contacts therefrom having a configuration which minimizes current density and path length therein while providing further mechanical advantages.

Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in poor RC time constants of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated or substantially reduced by selectively providing an etch-resistant masking material at thinner, i.e., recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second and third dielectric layers deposited over the planarized surface. The second and third dielectric layers are selected such that the second dielectric layer etches at a substantially slower rate than the third dielectric layer, thereby serving as a partial etch stop layer preventing deleterious over-etching of the borderless via.

The image pickup system includes: MOS sensors arranged in an image pickup region of a semiconductor substrate in the form of a matrix and having photoelectric transfer layers; a peripheral circuit part formed in a region of the semiconductor substrate except for the image pickup region and having a driving circuit for driving the MOS sensors and a signal processing circuit for processing output signals from the MOS sensors; and microlenses, formed on the photoelectric transfer layers via a first insulating film, for condensing picture signals on the photoelectric transfer layers, wherein the driving circuit and the signal processing circuit in the peripheral circuit part are covered by a second insulating film, and the distance between the surface of the first insulating film and the semiconductor substrate is shorter than the distance between the surface of a second insulating film and the semiconductor substrate.

The invention discloses a three-dimensional NAND ferroelectric memory and a preparation method thereof, and the three-dimensional NAND ferroelectric memory comprises a substrate layer (1), a conductive layer (2) and a stacked layer which are sequentially stacked, and the stacked layer comprising a plurality of isolation layers and a plurality of control gate electrode layers which are stacked; anda plurality of channel groups, each channel group in the plurality of channel groups comprising two channels; the two channels being arranged in a manner of penetrating through the laminated layer; the bottom ends of the two channels being embedded into the conductive layer (2). The bottom ends of the two channels are communicated, a separation layer (6) for separating the control gate electrodelayers of the two channels is arranged between the two channels, and a buffer layer (7), a ferroelectric film layer (8), a channel layer (9) and a channel group (5) formed by connecting a plurality offerroelectric field effect transistors (13) in series are sequentially arranged on the inner walls of the channels. More compact wiring can be obtained through channel group arrangement of the memory, higher-density integration is realized, and the reliability is higher.

A memory includes at least one first substrate on which unit memory arrays are disposed as a matrix type, each unit memory array including unit memory cells disposed in an array, a second substrate stacked with the at least one first substrate, the second substrate including a sense amplifier region in which sense amplifiers configured to sense information stored in the unit memory cells are disposed, and a plurality of vertical conduction traces configured to electrically connect the at least one first substrate with the second substrate. The sense amplifier region is disposed in a memory region of the second substrate, wherein the memory region of the second substrate corresponds to the memory region of the first substrate.

The invention provides an optical right-angle reflector and a manufacture method thereof. The method is used for manufacturing the optical right-angle reflector on a monocrystal silicon substrate, and comprises the steps of forming an etching mask on the surface of the substrate, wherein the etching mask comprises an opening for exposing the surface of the substrate, and the substrate is the monocrystal silicon substrate; wet etching the substrate with the etching mask to form an etched groove, wherein the etched groove at least comprises two side walls perpendicular to each other, the two side walls are silicon (110) crystal faces, and an included angle between each of the two side walls and the surface of the substrate is 45 degrees; and covering optical reflecting layers on the two side walls of the etched groove to form the right-angle reflector in the etched groove. The optical right-angle reflector manufactured according to the method provided by the invention is good in optical quality, high in precision, small in size and low in cost, a multi-groove right-angle reflector array can be conveniently manufactured, and thus the right-angle reflectors with large area can be acquired.

An optical connector capable of providing a multicore ferrule for optical communication or a fiber array for optical communication having a high dimensional accuracy and easily manufactured at a low cost, comprising a plurality of insert holes for inserting optical fibers therein arranged at specified intervals, characterized in that the accuracy of the center-to-center distances between the adjacent insert holes is within ±0.5 μm and a parallelism between the adjacent insert holes in hole axial direction is within ±0.1°.

The invention discloses a graphene-based waveguide integrated multimode electro-optic modulator and a manufacturing method thereof. The modulator comprises a first graphene nanoribbon layer, a secondgraphene nanoribbon layer, an insulator cladding, a multimode ridge waveguide, a first electrode pair, a second electrode pair, a third electrode pair, an insulating layer and a substrate layer, wherein the multimode ridge waveguide supports two transverse electric modes (TE), that is, a TE0 mode and a TE1 mode are simultaneously transmitted; the first graphene nanoribbon layer and the second graphene nanoribbon layer are integrated above the multimode ridge waveguide; the insulator cladding is used to achieve electrical isolation of the multimode ridge waveguide from the first graphene nanoribbon layer and the second graphene nanoribbon layer; the first electrode pair is connected to the first graphene nanoribbon layer, the second electrode pair is connected to the second graphene nanoribbon layer, and the third electrode pair is coupled to the multimode ridge waveguide for providing a back gate voltage to the graphene.