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Semiconductor structure, forming method and mask

A semiconductor and mask technology, applied in the direction of semiconductor devices, transistors, electric solid devices, etc., can solve the problems of poor overall performance of semiconductor devices, achieve the effects of improving overlay accuracy, improving electrical performance, and reducing process difficulty

Pending Publication Date: 2022-02-18
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
  • Description
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  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the performance of the SRAM in the semiconductor device formed in the prior art needs to be further improved, so that the overall performance of the semiconductor device is poor

Method used

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  • Semiconductor structure, forming method and mask
  • Semiconductor structure, forming method and mask
  • Semiconductor structure, forming method and mask

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Embodiment Construction

[0020] Currently formed semiconductor structures still suffer from poor performance. The reasons for the poor performance of the device are analyzed in conjunction with a method of forming a semiconductor structure.

[0021] refer to Figure 1 to Figure 5 It is a structural schematic diagram corresponding to each step in a method for forming a semiconductor structure.

[0022] Such as figure 1 and figure 2 as shown, figure 2 I and III in are the profiles at aa, figure 2 II in is a cross-sectional view at bb, providing a base, which includes a substrate 1, a fin 2 separated on the substrate 1, a dummy gate structure 3 across the fin 2, and a dummy gate structure located on the The source-drain doped layer 4 in the fin 2 on both sides of the dummy gate structure 3, the dummy gate structure 3 covers part of the top wall and part of the side wall of the fin 2, and the base includes The first device region I, the dummy device region IV, the second device region II and the ...

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Abstract

The invention discloses a semiconductor structure, a forming method and a mask, and the method comprises the steps: providing a substrate, wherein the substrate comprises a first device region, a pseudo device region, a second device region and a third device region which are sequentially arranged along a first row, and a third device region, a second device region, a pseudo device region and a first device region which are sequentially arranged along a second row. The first device region, the pseudo device region, the second device region and the third device region in the first row are in central symmetry with the first device region, the pseudo device region, the second device region and the third device region in the second row respectively According to the embodiment of the invention, a first shielding layer exposes the first device region and the pseudo device region, and the exposed area of the first shielding layer is large, so that the process window of the first shielding layer is large, the process difficulty of forming the first shielding layer is reduced, and the overlay precision of the first shielding layer is improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure, a forming method, and a mask. Background technique [0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of semiconductor technology, storage devices are more widely used, and the storage device and other device regions need to be formed on a chip at the same time to form an embedded semiconductor storage device. For example, to embed the storage device in the central processing unit, it is necessary to make the storage device compatible with the embedded central processing unit platform, and maintain the specifications and corresponding electrical performance of the original storage device. [0003] Gene...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11H01L27/02H01L29/423H10B10/00
CPCH01L27/0207H01L29/42356H10B10/18H10B10/12
Inventor 王楠
Owner SEMICON MFG INT (SHANGHAI) CORP
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