Transistor and manufacturing method thereof

Abstract

The invention discloses a transistor. The transistor comprises a base with a channel region, a source region, a drain region, a gate high-K dielectric layer and an interface layer, wherein the source region and the drain region are positioned at the two ends of the channel region of the base; the gate high-K dielectric layer is formed on a top layer of the base above the channel region between the source region and the drain region; the interface layer is positioned below the gate high-K dielectric layer; a first part of the interface layer is close to a source, and a second part of the interface layer is close to a drain; and an equivalent oxide layer of the first part is thicker than an equivalent oxide layer of a second layer. An asymmetric interface layer is formed by an asymmetrically substituted metal gate and is thinner on the side of the drain and is thicker on the side of the source. A short channel effect is more important on the thinner drain side, and the asymmetric interface layer contributes to controlling the short channel effect; and on the thicker source side, carrier mobility has larger influence on a device, and the asymmetric interface layer can prevent a carrier mobility rate from being reduced. In addition, the asymmetrically substituted metal gate can also form an asymmetric metal work function.

Description

technical field [0001] The present invention mainly relates to a transistor, especially a transistor with an asymmetric gate structure and a manufacturing method thereof. Background technique [0002] The main problem limiting the further scaling of metal-oxide-semiconductor (MOS) transistors is the short-channel effect (SCE), and this phenomenon mainly occurs when the channel length is less than 0.1 micron. Device failures include, but are not limited to, DIBL (lower drain-induced carrier barrier, ie, low source-drain breakdown voltage), subthreshold leakage, and threshold instability. These problems are collectively referred to as the short channel effect, which is mainly related to the equivalent oxide thickness (EOT) of the interface layer, and a thin EOT is beneficial to control the short channel effect (especially at the drain end), as cited in the citation High-Performance High- K / Metal Gates for 45nm CMOS and Beyond with Gate-First Processing (M. Chudziket al. VLSI ...

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This shows that the interface layer will cause the decrease of carrier mobility

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