Semiconductor device and forming method of semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device. The method includes the following steps that: a semiconductor substrate is provided, an opening is formed in the substrate, and the opening is formed by removing a dummy gate; metal work function layers are formed at the internal wall of the opening; ion implantation of a certain angle is carried out, so that threshold voltage corresponding to a metal work function layer at one side of a source region is larger than threshold voltage corresponding to a metal work function layer at one side of a drain region; and other grid layers are filled. According to the manufacturing method of the invention, voltage drop of a channel region near a source end is increased, and voltage drop of a channel region near a drain end is decreased, and therefore, the electric field of the drain end can be decreased, and short-channel effects such as DIBL (drain induced barrier lowering) can be suppressed, and the electric field of the source end is increased, so that the transport speed of carriers can be improved, and the performance of the device can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a semiconductor device and a forming method thereof. Background technique [0002] With the high integration of semiconductor devices, the channel length of the device continues to shrink, and the short channel effect becomes more and more significant. The short channel effect will deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in signal-to-noise ratio. and other issues become the dominant factors affecting device performance. [0003] The DIBL (Drain Induced Barrier Lowering) effect, that is, the barrier lowering effect introduced by the drain, is one of the short channel effects. After the channel length decreases and the voltage Vds increases, the depletion layer of the drain and source junctions Closer, the barrier height of the source terminal decreases, so ...

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Problems solved by technology

[0002] With the high integration of semiconductor devices, the channel length of the device continues to shrink, and the short channel effect becomes more and more significant. The short channel effect will deteriorate the electrical performance of the device, such as causing a decrease in the gate threshold voltage, an increase in power consumption, and a decrease in signal-to-noise ratio. and other issues become the dominant factors affecting device performance

[0003] The DIBL (Drain Induced Barrier Lowering) effect, that is, the barrier lowering effect introduced by the drain, is one of the short channel effects. After the channel length decreases and the voltage Vds increases, the depletion layer of the drain and source junctions Closer, the barrier height of the source terminal decreases, so the number of electrons injected into the channel by the source region increases, and the drain current increases, which reduces the threshold voltage of the device and affects the overall performance of the device. Moreover, as the size of the device continues to decrease, The DIBL effect is more severe

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