Semiconductor device manufacturing method

Abstract

The invention discloses a semiconductor device manufacturing method, which comprises steps: multiple first gate grooves and multiple second gate grooves are formed in a substrate; gate dielectric layers are formed in the multiple first gate grooves and the multiple second gate grooves; a second metal work function adjustment layer is formed on each gate dielectric layer; thicknesses of the second metal work function adjustment layers in the multiple first gate grooves are selectively adjusted; a first metal work function adjustment layer is formed on each second metal work function adjustment layer; a diffusion barrier layer is formed on the first metal work function adjustment layer; and a gate metal layer is formed on the diffusion barrier layer. According to the semiconductor device manufacturing method of the invention, through selectively depositing / etching the multiple metal work function layers on different device areas, the CMOS integrated technology is simplified, multi-threshold voltage regulation and control can be realized, and performance of the device is further improved.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor device, in particular to a CMOS integration method of a semiconductor device. Background technique [0002] As the feature size of CMOS devices shrinks to the 22nm technology node and below, the material selection, preparation and equivalent work function adjustment of the metal gate stack structure of high-k gate dielectric / metal gate MOS devices are all technical difficulties. [0003] In order to meet the needs of the device, a double metal gate structure is generally used, that is: NMOFET uses materials with low metal work function such as titanium aluminum as the metal work function layer, and PMOSFET uses materials with high metal work function such as titanium nitride as the metal work function layer . However, the choice of double metal gate material greatly increases the difficulty of CMOS integration, especially the gate stack filling holes prepared by the gate-last process a...

AI Technical Summary

Problems solved by technology

However, the choice of double metal gate material greatly increases the difficulty of CMOS integration, especially the gate stack filling holes prepared by the gate-last process are getting smaller and smaller, making it more and more difficult to fill the metal gate material, and the thickness of the metal gate stack The requirements are getting higher and higher

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