Resistive gate tunneling field effect transistor and preparation method thereof

Abstract

Disclosed is a resistive gate tunneling field effect transistor. The resistive gate tunneling field effect transistor comprises a control gate layer, a gate medium layer, a semiconductor substrate, a tunneling source area, a low-doped leakage area and a channel region. A control gate employs a gate stack structure and is successively composed of a bottom electrode layer, a volatile resistive material layer and a top electrode layer. The volatile resistive material layer is a material layer with a volatile resistive characteristic. The channel region is disposed above the tunneling source area and is partially overlapped with the tunneling source area in terms of position, a tunneling junction is formed at the interface of the channel region and the tunneling source area; the low-doped leakage area is disposed at the other side of the horizontal direction of the control gate and is spaced from the control gate by a horizontal interval; the low-doped leakage area and the tunneling source area are doped with impurities of different doping types; and the doping types of the semiconductor substrate and the channel region are consistent with that of the tunneling source area. The structure has large on-state currents and a steep subthreshold slope, and can satisfy the application demand of a low-voltage low-power logic device and a logic circuit when working under the condition of low bias.

Description

technical field [0001] The invention belongs to the field of field effect transistor logic devices and circuits in CMOS ultra large integrated circuits (ULSI), and in particular relates to a resistive gate tunneling field effect transistor and a preparation method thereof. Background technique [0002] As the size of metal-oxide-silicon field-effect transistors (MOSFETs) continues to shrink, especially when the feature size of the device enters the nanometer scale, the negative effects of the short channel effect of the device become more and more obvious. Drain-induced barrier-lowering effect (DIBL) and band-band tunneling effect increase the off-state leakage current of the device, which increases the power consumption of the integrated circuit along with the decrease of the threshold voltage of the device. And the subthreshold current conduction of traditional MOSFET devices is limited by the diffusion mechanism, and the limit value of the subthreshold slope at room tempe...

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Problems solved by technology

However, the device's switching speed, operating times and integration issues cannot be ignored.

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