Heterogeneous gate tunneling transistor and forming method thereof

Abstract

The invention provides a structure of a heterogeneous gate tunneling transistor of an under-gate process and a forming method of the heterogeneous gate tunneling transistor. The heterogeneous gate tunneling transistor comprises a substrate, a channel region, a source region, a drain region and a gate stack, wherein the channel region is formed in the substrate; the source region and the drain region are arranged on the two sides of the channel region; the doping types of the source region and the drain region are reverse; the gate stack is formed on the channel region and comprises a gate dielectric layer, a first gate electrode, a second gate electrode, a first vacuum side wall and a second vacuum side wall; the first gate electrode and the second gate electrode are formed on the gate dielectric layer and have different work functions; and the first vacuum side wall and the second vacuum side wall are formed on the two sides of the first gate electrode and the second gate electrode. Since the vacuum side wall from the gate to the drain region is introduced, the control of the gate over the drain region is weakened, and the gate-drain capacitance is reduced; a certain distance which can be accurately controlled exists between the gate stack and the drain region of a device, so that a tunneling potential barrier path is increased, and a double-pole window is expanded; and the energy band distribution of the channel region is modulated by a work function structure of the transverse heterogeneous gate, so that the sub-threshold slope of a transistor is obviously reduced, the driving current is increased and the performance of the device is enhanced.

Description

technical field [0001] The invention relates to the technical field of design and manufacture of semiconductor devices, in particular to a heterogeneous gate tunneling transistor with a vacuum or air sidewall and a gate-drain spacer structure based on a gate-last process and a forming method thereof. Background technique [0002] As the feature size continues to scale down, the size of a single transistor gradually reaches the dual limits of physics and technology. Integrated circuits face many small-size effects caused by materials and basic principles of devices, resulting in deterioration of device performance. For this reason, people have proposed improvements Among them, the tunneling field effect transistor (Tunneling Field Effect Transistor, TFET) is particularly prominent. As the size of tunneling field effect transistors is getting smaller and smaller, especially for narrow energy band materials, such as Ge, InAs, InSb and other materials, the traditional structure ...

AI Technical Summary

Problems solved by technology

As the size of tunneling field effect transistors is getting smaller and smaller, especially for narrow energy band materials, such as Ge, InAs, InSb and other materials, the traditional structure cannot well suppress the Ambipolar effect (bipolar conduction effect) of the device. ), leading to a sharp rise in the off-state current; at the same time, with the reduction of the feature size, the capacitance of the device, especially the gate-to-drain capacitance Cgd, takes a larger proportion, which makes the operating speed of the device decrease

The shortcoming of current prior art is that the performance of TFET device still needs to be improved

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