Green field effect transistor and manufacturing method thereof

Abstract

The invention relates to a green field effect transistor and a manufacturing method thereof, wherein the green field effect transistor comprises a silicon on insulator, a source electrode, a drain electrode and a channel body, wherein the silicon on insulator comprises a silicon substrate as well as a buried oxide layer and top layer silicon which are sequentially located on the silicon substrate; the source electrode and the drain electrode are located in the top layer silicon and isolated from each other and have different doping types; the cylindrical channel body is located between the source electrode and the drain electrode and sequentially comprises a source connector and a pocket injection layer from a cylindrical core to outside, one end of the channel body is connected to the source electrode, and the other end of the channel body is connected to the drain electrode; the source connector is electrically connected with the source electrode, and the pocket injection layer is electrically connected with the drain electrode; and a grid electrode structure located on the surface of the pocket injection layer of the channel body comprises a grid dielectric layer and a grid electrode on the surface of the grid dielectric layer. The green field effect transistor has the advantages of high response speed and sensitive switching characteristic, satisfies the requirements of a small size scaled-down device on reducing energy consumption and avoids generating a series of second-order effects.

Description

technical field

[0001] The invention relates to a field effect transistor, in particular to a green field effect transistor and a manufacturing method thereof. Background technique

[0002] In the development process of semiconductor VLSI, under the guidance of scaling of CMOS devices, the density and performance of transistors have been continuously and systematically increased following Moore's law. However, when the semiconductor industry develops to the 45nm node or smaller, the power consumption and power consumption density of chips have gradually become a problem that needs to be solved urgently. The power supply voltage has maintained 5V as the standard for all levels of technology for a long time. Therefore, scaling down the external voltage source (VDD-scaling) has increasingly become a bottleneck restricting the development of metal oxide field effect transistors (MOSFETs).

[0003] At present, it has been proposed that the use of gate bias in metal-oxide field-...

Examples

Embodiment Construction

[0045] It is known from the prior art that green transistors have lower energy consumption and stable device characteristics in a small size, which meets the low energy consumption requirements of VDD scaling down. On this basis, the present invention provides a new green field effect transistor.

[0046] Figure 4 It is a schematic diagram of the cross-sectional structure of the green field effect transistor provided by the present invention. include:

[0047] A silicon-on-insulator 10, the silicon-on-insulator includes a silicon substrate 100, a buried oxide layer 110 and a top layer of silicon 101 sequentially located on the silicon substrate 100;

[0048] The source 1 and the drain 2 are isolated from each other and have different doping types in the top silicon layer 101;

[0049] The channel body located between the source 1 and the drain 2, the channel body is cylindrical, one end is connected to the source 1, the other end is connected to the drain 2, and it include...

technical field

[0001] The invention relates to a field effect transistor, in particular to a green field effect transistor and a manufacturing method thereof. Background technique

[0002] In the development process of semiconductor VLSI, under the guidance of scaling of CMOS devices, the density and performance of transistors have been continuously and systematically increased following Moore's law. However, when the semiconductor industry develops to the 45nm node or smaller, the power consumption and power consumption density of chips have gradually become a problem that needs to be solved urgently. The power supply voltage has maintained 5V as the standard for all levels of technology for a long time. Therefore, scaling down the external voltage source (VDD-scaling) has increasingly become a bottleneck restricting the development of metal oxide field effect transistors (MOSFETs).

[0003] At present, it has been proposed that the use of gate bias in metal-oxide field-...

Examples

Embodiment Construction

[0045] It is known from the prior art that green transistors have lower energy consumption and stable device characteristics in a small size, which meets the low energy consumption requirements of VDD scaling down. On this basis, the present invention provides a new green field effect transistor.

[0046] Figure 4 It is a schematic diagram of the cross-sectional structure of the green field effect transistor provided by the present invention. include:

[0047] A silicon-on-insulator 10, the silicon-on-insulator includes a silicon substrate 100, a buried oxide layer 110 and a top layer of silicon 101 sequentially located on the silicon substrate 100;

[0048] The source 1 and the drain 2 are isolated from each other and have different doping types in the top silicon layer 101;

[0049] The channel body located between the source 1 and the drain 2, the channel body is cylindrical, one end is connected to the source 1, the other end is connected to the drain 2, and it include...

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