Ferroelectric field effect transistor based on GeSn material, and preparation method for ferroelectric field effect transistor

Abstract

The invention discloses a ferroelectric field effect transistor based on a GeSn material, and a preparation method for the ferroelectric field effect transistor, and solves problems that a conventional ferroelectric field effect transistor is small in conduction current and is larger in subthreshold swing. The ferroelectric field effect transistor comprises a substrate 1, a source electrode 2, a trench 3, a drain electrode 4, an insulating dielectric film 5, an internal grid electrode 6, a ferroelectric grid dielectric layer 7, and a grid electrode 8. The trench 3 is located at the center above the substrate 1, and the source electrode 2 and the drain electrode 4 are located at two sides of the trench 3. The insulating dielectric film 5, the internal grid electrode 6, the ferroelectric grid dielectric layer 7 and the grid electrode 8 are sequentially distributed above the trench 3 from the bottom to the top in a vertical manner. According to the invention, the GeSn material is introduced as the trench material of the transistor, thereby enabling the transistor to be able to obtain a smaller subthreshold swing and a higher switching speed at a low working voltage.

Description

technical field [0001] The invention belongs to the technical field of electronics, and further relates to a GeSn material-based ferroelectric field effect transistor and a preparation method thereof in the technical field of microelectronic devices. The invention can be used in large-scale integrated circuits with high performance and low power consumption. Background technique [0002] With the development of integrated circuits, the feature size of chips has been continuously reduced, and the integration level on a single chip has increased accordingly, and the resulting power consumption problem has become more and more serious. According to ITRS data, when the feature size is reduced to the 32nm node, the power consumption will be 8 times the expected trend, that is, with the gradual reduction of the feature size, traditional MOS devices will not be able to meet the performance requirements in terms of power consumption. In addition, the reduction of MOSFET size is lim...

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Problems solved by technology

However, the disadvantage of the MFIS-FET structure is that the electron mobility of silicon, the material used for the substrate, is low, which leads to a small conduction current of the transistor, and it becomes difficult to further reduce the subthreshold swing. Therefore, the switching speed of the transistor cannot be increased, and the application requirements of high-performance devices cannot be met.

However, there are still deficiencies that the transistor cannot reduce the operating voltage while increasing the conduction current of the transistor, resulting in high power consumption of the transistor, and cannot reduce the subthreshold swing and increase the switching speed of the transistor.

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