Ultra steep average subthreshold swing nano wire tunneling field effect transistor and method for preparing same

A tunneling field effect and transistor technology, applied in nanotechnology, semiconductor/solid-state device manufacturing, diodes, etc., can solve the problems of unfavorable TFET device application and high subthreshold slope of the device, and reduce the average subthreshold slope and large band The effect of tunneling current increment and simplified process flow

Active Publication Date: 2015-08-12
PEKING UNIV
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Problems solved by technology

[0003] However, unlike traditional MOSFETs, the subthreshold slope in the subthreshold region of the TFET transfer curve changes and gradually increases with the increase of the gate voltage, which leads to a TFET transfer characteristic lower than 60mV / dec The corresponding range of subthreshold slope is small, and the average subthreshold slope of the device is relatively high, which is not conducive to the application of TFET devices in the field of ultra-low power consumption

Method used

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  • Ultra steep average subthreshold swing nano wire tunneling field effect transistor and method for preparing same
  • Ultra steep average subthreshold swing nano wire tunneling field effect transistor and method for preparing same
  • Ultra steep average subthreshold swing nano wire tunneling field effect transistor and method for preparing same

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Embodiment Construction

[0041] The implementation method of the ultra-steep average sub-threshold swing nanowire tunneling field-effect transistor of the present invention will be further described through specific embodiments below in conjunction with the accompanying drawings.

[0042] The specific implementation steps are as Figure 2-Figure 8 Shown: (This example takes N-type devices as an example, and P-type devices can be deduced by analogy)

[0043] 1. Prepare the substrate material, which is an insulator (SiO 2 )1 on undoped Ge with crystal orientation , such as figure 2 shown.

[0044] 2, photolithography and etching form the nanowire core layer 2, and annealing (H 2 , 900°C, 5min), the diameter of the nanowire core layer is about 5nm-10nm, such as image 3 shown.

[0045] 3. Hydrofluoric acid is used to selectively etch the bottom of the nanowire core layer to form a groove with a depth of about 100nm, such as Figure 4 shown.

[0046] 4. On the nanowire core layer 2, epitaxy select...

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Abstract

The present invention provides an ultra steep average subthreshold swing nano wire tunneling field effect transistor and a method for preparing the same which belong to the field effect transistor logic device field of the CMOS ultra large scale integration (ULSI). The tunneling field effect transistor adopts a nano wire structure of core-multilayered shell, and the material band gap of a multilayered shell part is increased continuously along the radius direction of the nano wire. According to the present invention, a subthreshold slope degradation phenomenon in a device transfer characteristic can be restrained effectively, at the same time, an average subthreshold slope of the tunneling field effect transistor is reduced remarkably, and a more steep minimum subthreshold slope is kept.

Description

technical field [0001] The invention belongs to the field of CMOS ultra-large scale integrated circuit (ULSI) field-effect transistor logic devices, and in particular relates to an ultra-steep average subthreshold swing nanowire tunneling field-effect transistor and a preparation method thereof. Background technique [0002] Since the birth of integrated circuits, microelectronics integration technology has been developing continuously in accordance with "Moore's Law", and the size of semiconductor devices has been continuously reduced. As semiconductor devices enter the deep submicron range, traditional MOSFET devices are limited by the conduction mechanism of self-diffusion drift, and the subthreshold slope is limited by the thermoelectric potential kT / q, which cannot be reduced synchronously with the reduction of device size. As a result, the reduction of leakage current of MOSFET devices cannot meet the requirements of device size reduction, the energy consumption of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/739H01L29/08H01L29/10H01L29/06H01L21/331B82Y40/00
CPCB82Y40/00H01L29/0673H01L29/0847H01L29/1033H01L29/66356H01L29/7391
Inventor 黄如吴春蕾黄芊芊樊捷闻王阳元
Owner PEKING UNIV
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