Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology

A field effect tube and anti-irradiation technology, applied in transistors, electrical components, circuits, etc., can solve problems that threaten circuit and system reliability, drift of device threshold voltage, increase of off-state leakage current, etc., and achieve strong anti-total dose Irradiation capability, off-state leakage current reduction, effect of leakage current reduction

Inactive Publication Date: 2015-09-23
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The parasitic channel introduced by shallow trench isolation STI will lead to device threshold voltage drift, subthreshold swing degradation and off-state leakage current increase, and even when the total dose accumulates to a certain level, the channel cannot be turned off normally and the device will fail, seriously threatening the circuit and system reliability

Method used

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  • Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology
  • Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology
  • Gate-all-around anti-irradiation MOS field effect transistor based on 65 nm technology

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0045] Example 1, making a 65nm MOS field effect transistor with a square gate ring.

[0046] Step 1, growing an epitaxial layer.

[0047] 1.1) Using the method of chemical vapor deposition at a temperature of 650 ° C with SiH 4 An epitaxial layer with a thickness of 1200nm is grown on a P-type substrate as a reactant;

[0048] 1.2) The depth of the epitaxial layer is 150nm, the concentration is 1×10 18 cm -3 doping to adjust the channel concentration.

[0049] Step 2, etching the isolation groove.

[0050] 2.1) Thin SiO with a thickness of 10nm is thermally oxidized on the epitaxial layer at a temperature of 1250°C by dry oxygen process 2 buffer layer, then the SiO 2 25nm thick Si grown on the buffer layer 3 N 4 The protective layer;

[0051] 2.2) In Si 3 N 4 A layer of photoresist is made on the protective layer, and the Si 3 N 4 Make a square ring-shaped isolation groove window on the photoresist around the protective layer and etch to form an isolation groove ...

example 2

[0071] Example 2, manufacturing a 65nm MOS field effect transistor with a rectangular gate ring.

[0072] Step 1, using chemical vapor deposition method at a temperature of 600 ° C with SiH 4 An epitaxial layer with a thickness of 900nm was grown on a P-type substrate as a reactant, and then the depth of the epitaxial layer was 125nm, and the concentration was 7×10 17 cm -3 doping to adjust the channel concentration.

[0073] Step 2, etching the isolation groove.

[0074] Thin SiO with a thickness of 8 nm was grown by thermal oxidation at a temperature of 1200 °C on the epitaxial layer by a dry oxygen process 2 buffer layer, then the SiO 2 22nm thick Si grown on the buffer layer 3 N 4 protective layer; in Si 3 N 4 A layer of photoresist is made on the protective layer, and the Si 3 N 4 Make a rectangular ring-shaped isolation groove window on the photoresist around the protective layer and etch to form an isolation groove with a width of 400nm; after the etching is c...

example 3

[0086] Example 3, manufacturing a 65nm MOS field effect transistor with a circular gate ring.

[0087] Step A, growing an epitaxial layer.

[0088] A1) using chemical vapor deposition method at a temperature of 550 ° C with SiH 4 An epitaxial layer with a thickness of 600nm is grown on a P-type substrate as a reactant;

[0089] A2) The depth of the epitaxial layer is 100nm, the concentration is 2×10 17 cm -3 doping to adjust the channel concentration.

[0090] Step B, etching the isolation groove.

[0091] B1) Thin SiO with a thickness of 5 nm is thermally oxidized on the epitaxial layer at a temperature of 1100 ° C by a dry oxygen process 2 buffer layer, on SiO 2 20nm thick Si grown on the buffer layer 3 N 4 The protective layer;

[0092] B2) in Si 3 N 4 A layer of photoresist is made on the protective layer, and the Si 3 N 4 A circular ring-shaped isolation groove window is made on the photoresist around the protective layer and etched to form an isolation groov...

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Abstract

The present invention discloses a gate-all-around anti-irradiation MOS field effect transistor based on a 65 nm technology for mainly solving the problems of threshold voltage drift, subthreshold swing degeneration and off-state leakage current degeneration of a conventional 65 nm MOS field effect transistor under a total dose radiation environment. The gate-all-around anti-irradiation MOS field effect transistor based on the 65 nm technology comprises a P-type substrate (1) and an epitaxial layer (2) located on the substrate, a drain region (3) is arranged in the middle of the epitaxial layer, and a grid (4) is arranged above the epitaxial layer adjacent to the periphery of the drain region (3). Light doping source drain regions (5) are arranged in the epitaxial layer below the boundaries at the inner and outer sides of the grid, an area between the light doping source drain regions forms a channel, and a source region (6) is arranged in the epitaxial layer adjacent to the periphery of the grid. An isolating groove (7) is arranged in the epitaxial layer adjacent to the periphery of source region, and a grating ring, a source ring and an isolating groove ring sleeve structure surrounding the exterior of an active region orderly are formed. The gate-all-around anti-irradiation MOS field effect transistor based on the 65 nm technology of the present invention enables the device anti-total dose radiation capability to be improved, and can be used to manufacture a large-scale integrated circuit.

Description

technical field [0001] The invention belongs to the technical field of semiconductor devices, in particular to a 65nm MOS field-effect transistor resistant to total dose radiation, which can be used in the preparation of large-scale integrated circuits. Background technique [0002] Since the first discovery of the ionizing radiation effect of metal oxide semiconductor field effect transistor MOSFET in 1964, the total dose effect of ionizing radiation has been one of the most important factors leading to functional degradation of electronic system devices and circuits for space applications. The total dose effect refers to the effect that when ionizing radiation particles with energy greater than the forbidden band width of the semiconductor irradiate the semiconductor, some bound state electrons inside the semiconductor absorb the energy of the radiation particles and are excited to the conduction band to generate electron-hole pairs. Studies have shown that the total dose ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/423H01L21/28H01L21/336
CPCH01L29/78H01L29/42356H01L29/66568
Inventor 刘红侠陈树鹏张丹陈煜海刘永杰王倩琼赵东东汪星
Owner XIDIAN UNIV
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