Ferroelectric/piezoelectric field effect transistor and preparation method thereof

Abstract

The invention provides a ferroelectric /piezoelectric field effect transistor and a preparation method thereof. The iron/piezoelectric field effect transistor comprises a substrate, a source electrode, a drain electrode and a gate electrode. The gate electrode comprises silicon dioxide, a high dielectric layer, a piezoelectric material layer, a titanium nitride layer, a ferroelectric material layer and a tantalum nitride layer, which are sequentially stacked from bottom to top. The preparation method comprises the following steps: providing a silicon substrate, and doping P-type ions into thesilicon substrate to form a substrate; forming a source electrode and a drain electrode at two sides of the substrate; sequentially forming the silicon dioxide layer and the high dielectric layer between the source electrode and the drain electrode above the substrate; and sequentially forming the piezoelectric material layer, the titanium nitride layer, the ferroelectric material layer and the tantalum nitride layer on the high dielectric layer. Based on the field effect transistor, the ferroelectric material and the piezoelectric material are introduced into the gate electrode, and the negative capacitance effect of the ferroelectric material and the electrostrictive effect of the piezoelectric material are used for jointly achieving the voltage amplification function. The working voltage of the device is reduced, the subthreshold swing is reduced, the on/off speed of the device is improved, and the working power consumption is further reduced.

Description

technical field [0001] The invention relates to the field of design and manufacture of semiconductor devices, in particular to an iron / piezoelectric field effect transistor and a preparation method thereof. Background technique [0002] With the improvement of the integration density of CMOS devices, the increasing power consumption will become an important bottleneck restricting the further development of integrated circuits. Reducing the operating voltage by reducing the sub-threshold swing of the device is an effective means to reduce the power consumption. The field effect transistor with negative capacitance effect is an effective technical solution to realize this purpose. [0003] At present, the sub-threshold swing value is reduced by adjusting the gate oxide layer structure and thickness composition, channel structure and material, thereby reducing device power consumption. However, none of these methods can make the subthreshold swing smaller than 60mV / decade (an...

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However, none of these methods can make the sub-thresh

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