A radio frequency millimeter-wave phase-to-voltage converter

Abstract

This invention discloses a radio frequency millimeter-wave phase-to-voltage converter, belonging to the field of radio frequency microwave integrated circuit technology. The converter includes: a first and second frequency divider chain for dividing two input signals to achieve phase compression; a first and second quadrature generator for providing a -90° linearized bias; a three-state coupling network connected between the two frequency divider chains to eliminate phase mode ambiguity introduced by the frequency dividers through reconfigurable coupled phase; and a symmetrical phase detector for converting the linearized phase difference into a voltage signal output. This invention compresses the ±180° phase difference to a small angle range using phase compression technology, combined with linearized bias to allow the phase detector to operate in the linear region, and utilizes the three-state coupling network to achieve unambiguous detection across the entire 360° phase range. Implemented using a 40nm CMOS process, it requires no external clock, has no inductor design, a core area of ​​only 0.016mm², power consumption of 22mW, a response speed of 120ns, and a linearity of 1.05% FSR.

Description

Technical Field

[0001] This invention relates to the field of radio frequency microwave integrated circuit technology, and in particular to a radio frequency millimeter-wave phase-to-voltage converter. Background Technology

[0002] Radio frequency millimeter-wave communication systems, phased array radars, high-speed clock data recovery circuits, and time-interleaved analog-to-digital converters, among other core radio frequency microwave modules, place extremely high demands on the accuracy, speed, and integration of phase detection and conversion. Phase detectors, as key units for achieving phase calibration, phase tracking, and beamforming, are widely used in 5G / 6G communications, millimeter-wave radar, and high-speed wired transmission systems. An ideal phase detection solution must meet comprehensive performance requirements including full 360° phase detection, high linearity, no external clock dependence, low power consumption, small area, and fast response.

[0003] In existing technologies, phase detection and conversion schemes are mainly divided into three categories: High-speed ADC direct sampling scheme: This scheme uses multiple high-speed ADCs to directly sample RF millimeter-wave signals, calculates the phase difference through digital signal processing, and converts it into a voltage signal. While the hardware architecture is simple, the ADCs and their associated DSPs have high hardware requirements, resulting in extremely high circuit power consumption and chip area overhead, low integration, and making it unsuitable for highly integrated RF millimeter-wave systems.

[0004] I / Q modulation detection scheme: The test signal is I / Q modulated to calculate the phase difference. Compared with the ADC scheme, it reduces power consumption and area. However, the inherent I / Q phase mismatch in the actual circuit will introduce significant phase detection error. In addition, it relies on an external down-conversion clock, which limits the flexibility and integration of the circuit. The linearity of phase conversion is difficult to guarantee.

[0005] Phase-to-digital converter solution: It downconverts the RF phase to baseband through a high-precision external reference clock to achieve high-precision phase detection. However, it requires multiple high-precision external clocks, resulting in large chip area overhead and limited phase conversion response speed, which cannot meet the application requirements of dynamic phase tracking (such as fast frequency hopping phased array and adaptive equalization wired link).

[0006] Therefore, there is an urgent need for a radio frequency millimeter-wave phase-to-voltage converter that requires no external clock, has a full phase range, high linearity, low power consumption, small area, and fast response to overcome the shortcomings of existing technologies. Summary of the Invention

[0007] The purpose of this invention is to provide a radio frequency millimeter-wave phase-to-voltage converter to solve the problems of external clock dependence, mode ambiguity in full 360° phase detection, low linearity, high power consumption, large area, and slow response speed in traditional radio frequency millimeter-wave phase-to-voltage conversion schemes.

[0008] The technical solution of this invention is implemented as follows: A radio frequency millimeter-wave phase-to-voltage converter includes: a first frequency divider chain for receiving a first radio frequency millimeter-wave input signal and dividing the signal to compress its phase; a second frequency divider chain for receiving a second radio frequency millimeter-wave input signal and dividing the signal to compress its phase; a first quadrature generator whose input is connected to the output of the first frequency divider chain and outputs a first 0° and 90° quadrature signal; a second quadrature generator whose input is connected to the output of the second frequency divider chain and outputs a second 0° and 90° quadrature signal; a three-state coupling network connected between the first and second frequency divider chains and used to eliminate phase mode ambiguity generated by the first and second frequency divider chains during phase compression through reconfigurable coupled phase; and a symmetrical phase detector whose first input is connected to the output of the first quadrature generator and whose second input is connected to the output of the second quadrature generator, used to convert the phase difference of the two quadrature signals into a voltage signal output.

[0009] Optionally, the first and second frequency divider chains each include three cascaded CML latch structure frequency dividers. Each frequency divider outputs four orthogonal phases of 0°, 90°, 180°, and 270°. The three frequency dividers work together to achieve a phase compression ratio of N=8, compressing the input ±180° phase difference to ±22.5°.

[0010] Optionally, the first and second quadrature generators utilize the inherent quadrature output of the last-stage frequency divider to provide a -90° linearized bias, so that the input phase of the symmetrical phase detector falls within the linear monotonic region [-112.5°, -67.5°] of the cosine response.

[0011] Optionally, the tri-state coupling network includes three coupling channels: 0°, 90°, and -90°. The coupling capacitor is controlled by a MOSFET switch to switch the coupling phase θ between three states: 0°, θ>0°, and θ<0°, thereby eliminating phase mode ambiguity near ±180°.

[0012] Optionally, the three-state coupling network is connected after the first-stage frequency divider, and a fixed 0° coupling network is connected between the second-stage and third-stage frequency dividers to reduce the uncertainty of the phase mode from 8 to 2, thereby achieving unambiguous detection of the entire 360° phase range in conjunction with the three-state coupling network.

[0013] Optionally, the symmetrical phase detector adopts a differential symmetrical topology structure, consisting of a differential input stage, a current mirror load, and a differential output stage. It has an inductor-free design and a frequency-independent -90° fixed zero-crossing characteristic in the 18-23GHz frequency band. The output response matches an ideal cosine function.

[0014] Optionally, the converter is implemented based on a 40nm CMOS process, with a core circuit power supply voltage of 1.1V, a power consumption of 22mW, a core area of ​​0.016mm², a response settling time of 120ns, an operating frequency covering 18-23GHz, a linearity of 1.05% FSR, and a root mean square error of 0.67% FSR.

[0015] Optionally, the converter requires no external clock, has no inductor design, and features a fully self-contained architecture, making it compatible with RF millimeter-wave communication, phased array, millimeter-wave radar, and high-speed wired transmission systems.

[0016] The beneficial effects of this invention are: The radio frequency millimeter-wave phase-to-voltage converter proposed in this invention solves the core technical problems of traditional solutions through innovative architecture design including phase compression, linearized bias, three-state coupling network, and symmetrical phase detector, and has the following significant advantages: No external clock dependency: The fully self-contained architecture requires no external reference clock or down-conversion clock, which improves the flexibility and integration of the circuit and makes it suitable for highly integrated RF millimeter-wave systems.

[0017] 360° Full-Phase Unambiguous Detection: The three-state coupling network effectively solves the phase mode ambiguity problem of the frequency divider, realizing smooth and monotonic detection across the entire 360° phase range and eliminating detection discontinuities.

[0018] High linearity: The combination of phase compression and linearized bias technology with a symmetrical phase detector achieves a high linearity of 1.05% FSR, with a root mean square error as low as 0.67% FSR, resulting in high phase detection accuracy.

[0019] Implemented using a 40nm CMOS process, with an inductor-free design, a core area of ​​only 0.016mm², and a power consumption of only 22mW, which are 1 / 4 and 1 / 8 of those of traditional analog phase detection solutions, respectively, resulting in a significant improvement in integration.

[0020] Ultra-fast response: The response setup time is approximately 120ns, which is more than 10 times faster than traditional phase detection / conversion schemes. It can achieve dynamic phase tracking and is suitable for high-speed application scenarios such as fast frequency hopping phased arrays and adaptive equalization wired links.

[0021] Wide bandwidth adaptability: The operating frequency covers the 18-23GHz RF millimeter wave band, and the maximum output voltage fluctuation under fixed phase is only 0.20% FSR, and the root mean square fluctuation is 0.09% FSR, with high performance stability within the frequency band.

[0022] Compared with existing RF millimeter-wave phase detection solutions, this invention achieves significant breakthroughs in core indicators such as no external clock, linearity, power consumption, area, and response speed. Its overall performance far exceeds that of existing solutions, and it has extremely high engineering application value and industrialization prospects. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a high-speed ADC direct sampling architecture; Figure 2 This is a schematic diagram of an I / Q modulation detection scheme; Figure 3 This is a schematic diagram of a high-speed ADC direct sampling architecture; Figure 4 This is a schematic diagram of the overall architecture of a radio frequency millimeter-wave phase-to-voltage converter; Figure 5 This is a schematic diagram of the architecture and three working states of a three-state coupled network (TSCN); Figure 6 This is a schematic diagram of the topology of a symmetrical phase detector; Figure 7 This is a schematic diagram illustrating the implementation of a three-level phase compression network. Figure 8 This is a schematic diagram of the implementation of a three-state coupled network (TSCN). Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0026] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0027] Before explaining the structural principle of the radio frequency millimeter-wave phase-to-voltage converter described in this invention application, a brief description of the existing related technologies is necessary: The existing technical solution is: high-speed ADC direct sampling, as shown in the schematic diagram below. Figure 1 As shown, a multi-channel high-speed ADC directly samples the RF millimeter-wave signal, calculates the phase difference φ using digital signal processing (DSP), and converts it into a voltage signal without an external clock source. While this solution has a simple hardware architecture, it essentially shifts the burden of functionality to the ADC module and the subsequent DSP. Its disadvantages include: high hardware requirements for the high-speed ADC and its accompanying DSP, resulting in extremely high circuit power consumption and chip area overhead, low integration, and unsuitability for highly integrated RF millimeter-wave systems.

[0028] The technical solution of prior art 2: I / Q modulation detection scheme, the schematic diagram of which is shown below. Figure 2 As shown, this scheme uses I / Q modulation of the test signal to calculate the phase difference. Compared to the direct sampling scheme of ADC, it reduces power consumption and area, and does not require complex DSP processing. However, it relies on an external down-conversion clock for signal processing. Its disadvantages are: the inherent I / Q phase mismatch in the actual circuit will introduce significant phase detection errors, and the dependence on an external clock limits the flexibility and integration of the circuit, making it difficult to guarantee the linearity of the phase conversion.

[0029] The existing technical solution three is a phase-to-digital converter (PDC) solution, the schematic diagram of which is shown below. Figure 3 As shown, this scheme downconverts the RF phase to kHz baseband using a high-precision external reference clock, achieving high-precision phase detection, suitable for scenarios requiring high phase resolution. Its drawbacks are: it requires multiple high-precision external reference clocks, resulting in large chip area overhead, and its phase conversion response speed is limited, failing to meet the application requirements of dynamic phase tracking (such as fast frequency-hopping phased arrays and adaptive equalization wired links).

[0030] To address the technical problems of traditional RF millimeter-wave phase-to-voltage conversion schemes, such as external clock dependence, mode ambiguity in full 360° phase detection, low linearity, high power consumption, large area, and slow response speed, this invention proposes an RF millimeter-wave phase-to-voltage converter without an external clock. Through phase compression, linear bias compensation, and a three-state coupling network architecture design, it achieves phase-to-voltage conversion with 360° full-phase unambiguous detection, high linearity, low power consumption, small area, and ultra-fast response. At the same time, the circuit does not require an external clock and has no inductor design, which greatly improves the integration and adapts to the application requirements of high-speed, highly integrated systems such as RF millimeter-wave communication, phased array, and millimeter-wave radar.

[0031] Example 1:

[0032] Figure 4 This is a schematic diagram of the overall architecture of the radio frequency millimeter-wave phase-to-voltage converter of the present invention. Figure 4As shown, the phase-to-voltage converter in this embodiment includes: a first frequency divider chain, a second frequency divider chain, a first quadrature generator, a second quadrature generator, a three-state coupling network (TSCN), and a symmetrical phase detector (PD).

[0033] The first frequency divider chain receives the first RF millimeter-wave input signal IN1 at its input, and the second frequency divider chain receives the second RF millimeter-wave input signal IN2 at its input. Both the first and second frequency divider chains are composed of three cascaded current-mode logic (CML) latch-structure frequency dividers, such as... Figure 7 As shown. Each frequency divider outputs four quadrature phases: 0°, 90°, 180°, and 270°. The three frequency dividers work together to achieve a phase compression ratio of N=8, compressing the input ±180° phase difference to ±22.5°. While achieving phase compression, the inherent quadrature output of the last frequency divider in the frequency divider chain provides the quadrature signal basis for subsequent stages.

[0034] The input of the first quadrature generator is connected to the output of the first frequency divider chain, and the input of the second quadrature generator is connected to the output of the second frequency divider chain. The quadrature generator utilizes the quadrature output of the last-stage frequency divider to provide a -90° linearized bias to the compressed phase signal, ensuring that the phase detector's input phase falls within the linear monotonic region of the cosine response [-112.5°, -67.5°]. Specifically, the quadrature generator outputs two quadrature signals, 0° and 90°. The 90° output is equivalent to a +90° phase shift of the original signal. Combined with the quadrature characteristics of the frequency divider itself, the actual bias provided to the phase detector is -90°, thus shifting the phase detector's operating point to the linear region.

[0035] The tri-state coupling network connects between the first and second frequency divider chains, specifically after the first-stage frequency divider. The tri-state coupling network employs a reconfigurable capacitive coupling architecture, such as... Figure 8 As shown, it includes three coupling channels: 0°, 90°, and -90°. The 0° coupling is a fixed channel, while the 90° and -90° coupling channels are controllably enabled by controlling the on / off state of the MOSFET switches via voltages V90 and V-90. The effective coupling capacitance of the coupling network is adjusted by the MOSFET switches, allowing the coupling phase θ to switch between three states: 0°, θ>0°, and θ<0°. The three operating states are as follows: Figure 5 As shown: State 1 (θ=0°) achieves effective compression of most input phases, with invalid phase modes only existing around ±180°; State 2 (θ>0°) resolves phase ambiguity around -180°; State 3 (θ<0°) resolves phase ambiguity around +180°. A fixed 0° coupling network is connected between the second and third stage frequency dividers, reducing the phase mode uncertainty from 8 to 2. Combined with the three-state coupling network of the first stage, unambiguous detection across the entire 360° phase range is finally achieved.

[0036] The first input terminal of the symmetrical phase detector is connected to the output terminal of the first quadrature generator, and the second input terminal is connected to the output terminal of the second quadrature generator. The phase detector adopts a differential symmetrical topology, such as... Figure 6 As shown, the circuit consists of a differential input stage, a current mirror load, and a differential output stage, with no inductor. The symmetrical structure of the circuit ensures that the phase detector has a frequency-independent -90° fixed zero-crossing characteristic in the 18-23GHz frequency band. The input phase achieves fixed zero-crossing at -90°, and the output response accurately matches the ideal cosine function, providing a foundation for linear phase-to-voltage conversion.

[0037] The workflow of this embodiment is as follows: Two RF millimeter-wave input signals, IN1 and IN2, are respectively fed into the first and second frequency divider chains. Phase compression (N=8) is achieved through a three-stage frequency divider, compressing the ±180° phase difference to ±22.5°. The compressed signal is given a -90° linearized bias by an orthogonal generator, so that the input phase of the phase detector falls in the linear monotonic region. The three-state coupling network eliminates the phase mode ambiguity introduced by the frequency divider through state switching, ensuring a smooth and monotonic transition across the entire 360° phase range. The biased linear phase signal is fed into a symmetrical phase detector, which converts the linear phase difference into a differential voltage signal output. After amplification of the differential output voltage, the state switching of the three-state coupling network is used to fuse the output, reconstructing a continuous 360° phase-voltage conversion curve.

[0038] This embodiment is implemented based on a 40nm CMOS process, with a core circuit power supply voltage of 1.1V and a power consumption of only 22mW; the core area is only 0.016mm², and the inductor-free design further improves the integration density; the operating frequency covers the 18-23GHz RF millimeter wave band, achieving phase-to-voltage conversion in a 360° full phase range, with a linearity of 1.05% FSR, a root mean square error of 0.67% FSR, and a response settling time of approximately 120ns, which is more than 10 times faster than traditional solutions.

[0039] It should be noted that the number of stages in the frequency divider chain in this embodiment is not limited to three stages and can be adjusted according to the actual phase compression ratio requirements; the implementation method of the three-state coupling network is not limited to capacitive coupling, and other controllable phase shift structures can also be used; the quadrature generator can also be integrated into the last stage of the frequency divider. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the protection scope of this invention.

[0040] The radio frequency millimeter-wave phase-to-voltage converter described in this embodiment solves the core technical problems of traditional solutions through an innovative architecture design that incorporates phase compression, linearized bias, a three-state coupling network, and a symmetrical phase detector, resulting in the following significant advantages: No external clock dependency: The fully self-contained architecture requires no external reference clock or down-conversion clock, which improves the flexibility and integration of the circuit and makes it suitable for highly integrated RF millimeter-wave systems.

[0041] 360° Full-Phase Unambiguous Detection: The three-state coupling network effectively solves the phase mode ambiguity problem of the frequency divider, realizing smooth and monotonic detection across the entire 360° phase range and eliminating detection discontinuities.

[0042] High linearity: The combination of phase compression and linearized bias technology with a symmetrical phase detector achieves a high linearity of 1.05% FSR, with a root mean square error as low as 0.67% FSR, resulting in high phase detection accuracy.

[0043] Implemented using a 40nm CMOS process, with an inductor-free design, a core area of ​​only 0.016mm², and a power consumption of only 22mW, which are 1 / 4 and 1 / 8 of those of traditional analog phase detection solutions, respectively, resulting in a significant improvement in integration.

[0044] Ultra-fast response: The response setup time is approximately 120ns, which is more than 10 times faster than traditional phase detection / conversion schemes. It can achieve dynamic phase tracking and is suitable for high-speed application scenarios such as fast frequency hopping phased arrays and adaptive equalization wired links.

[0045] Wide bandwidth adaptability: The operating frequency covers the 18-23GHz RF millimeter wave band, and the maximum output voltage fluctuation under fixed phase is only 0.20% FSR, and the root mean square fluctuation is 0.09% FSR, with high performance stability within the frequency band.

[0046] Compared with existing RF millimeter-wave phase detection solutions, this invention achieves significant breakthroughs in core indicators such as no external clock, linearity, power consumption, area, and response speed. Its overall performance far exceeds that of existing solutions, and it has extremely high engineering application value and industrialization prospects.

[0047] Example 2:

[0048] This embodiment is based on Embodiment 1 and is used to further illustrate the principle of how the above structure achieves its effect: The proposed RF millimeter-wave phase-to-voltage converter is a fully self-contained architecture that requires no external clock and has no inductor design. Its core consists of four main modules: a frequency divider, an orthogonal generator, a three-state coupling network (TSCN), and a multiplier (mixer). The overall architecture is shown in Figure 4.

[0049] The core working principle of the circuit is as follows: 1) The phase compression mechanism of the distributor is used to compress the input 360° (±180°) RF millimeter wave phase difference to a small angle range; 2) The outputs of two channels, 0° and 90°, are respectively led out through the quadrature generator to shift the compressed phase to the linear monotonic region of the cosine response of the phase detector; 3) If the circuit has phase mode ambiguity problems, it can be solved by adding an inter-channel coupling network; 4) Finally, the linearized phase signal is converted into a voltage signal through the multiplier (mixer) to achieve linear phase-voltage conversion in the full phase range of 360°.

[0050] Phase compression and linearized bias principle: A phase compression network is constructed using multiple frequency dividers. Taking a three-stage divide-by-2 network as an example, the phase compression ratio N=2³=8, which can compress the input phase range from ±180° to ±22.5°. The inherent quadrature output of the last stage divider can be used to provide a -90° linearized bias to the compressed phase, ensuring that the phase detector's input phase falls within the linear monotonic region of the cosine response [-112.5°, -67.5°]. The phase detector's response function is: PD(φ) = cos(φ / N − π / 2) = sin(φ / N). When the phase compression ratio N is sufficiently large, the small-angle approximation sin(φ / N) ≈ φ / N holds, achieving linear phase-to-voltage conversion. A three-stage frequency divider (N=8) can improve the linearity from 2.1% FSR to 0.5% FSR compared to a two-stage frequency divider (N=4), significantly improving the linearity accuracy of the phase-to-voltage conversion.

[0051] Phase mode ambiguity cancellation in three-state coupled networks (TSCN): The frequency divider suffers from phase mode ambiguity during phase compression (two phase mappings for single-channel output and four phase combinations for dual-channel output), leading to discontinuities and errors in 360° phase detection. This invention introduces a three-state coupling network (TSCN), such as... Figure 5 As shown, unambiguous compression across the entire 360° phase range is achieved through three operating states of the reconfigurable coupled phase θ (θ=0°, θ>0°, θ<0°): State 1 (θ=0°): Achieves effective compression of most of the input phase, with invalid phase modes existing only around ±180°; State 2 (θ>0°): Resolves phase ambiguity near -180° and achieves correct phase compression near +180°; State 3 (θ<0°): Resolves phase ambiguity near +180° and achieves correct phase compression near -180°.

[0052] The three-state coupling network adjusts the effective coupling capacitance by switching MOSFETs to reconstruct the coupled phase θ, eliminates discontinuities in phase detection, and ensures smooth, monotonic phase-voltage conversion across the entire 360° phase range.

[0053] Symmetrical phase detector (PD) design: Abandoning the traditional Gilbert unit phase detector, a symmetrical cosine response phase detector architecture is adopted, such as... Figure 6 As shown, the phase detector is guaranteed to have frequency-independent zero-crossing characteristics (-90° fixed zero-crossing point) in the RF millimeter-wave band (18-23GHz), accurately tracking the ideal cosine response, avoiding the response deviation caused by frequency changes in traditional phase detectors, and further improving the linearity and accuracy of phase-to-voltage conversion.

[0054] Overall circuit workflow: Two radio frequency millimeter wave input signals (IN1, IN2) are fed into a cascaded CML phase-locked loop divider, and each divider generates four output phases from 0° to 270°. The first-stage frequency divider is connected to a three-state coupling network (TSCN), and the second and third-stage frequency dividers are connected to a fixed 0° coupling network to eliminate phase mode ambiguity and achieve unambiguous 360° phase compression. The three-stage frequency divider compresses the input phase to ±22.5° and provides a -90° linearized bias through its inherent quadrature output; The biased linear phase signal is fed into a symmetrical phase detector, which converts the linear phase difference into a differential voltage signal output. After amplifying the differential output voltage, the state switching of the three-state coupling network is combined with the output to reconstruct a continuous 360° phase-voltage conversion curve.

[0055] Example 3:

[0056] Based on Embodiment 2, a specific embodiment for implementing the technology of the present invention is disclosed: The radio frequency millimeter-wave phase-to-voltage converter of the present invention is implemented based on 40nm CMOS process. The specific implementation of each core module is as follows, taking into account the design requirements of low power consumption, small area and high performance.

[0057] Specific implementation method one: Implementation of a three-stage frequency divider phase compression network.

[0058] The phase compression network employs a three-stage cascaded CML phase-locked loop divider, such as... Figure 7As shown, each frequency divider stage consists of current-mode logic (CML) latches, which have the advantages of good high-frequency characteristics and low power consumption, and can be adapted to the RF millimeter-wave band. Each frequency divider stage generates four orthogonal output phases of 0°, 90°, 180°, and 270°, providing a basis for phase compression and linearized bias; the three frequency dividers work together to achieve a phase compression ratio of N=8, compressing the ±180° input phase to ±22.5°.

[0059] Specific implementation method two: Implementation of phase-free mode ambiguous coupling network.

[0060] Three-state coupled networks (TSCNs) employ a reconfigurable capacitively coupled architecture, such as... Figure 8 As shown, it includes three coupling channels: 0°, 90°, and -90°. The 0° coupling channel is a fixed channel, while the 90° and -90° coupling channels are controllably enabled by controlling the on / off state of the MOSFET switch through voltages V90 and V−90. By adjusting the effective coupling capacitance of the coupling network through the MOSFET switch, the coupling phase θ can be switched between three states: 0°, θ>0°, and θ<0°, thus eliminating phase mode ambiguity.

[0061] The second and third stage frequency dividers are connected to a fixed 0° coupling network, which reduces the uncertainty of the phase mode from 8 to 2. Together with the three-state coupling network of the first stage, it achieves unambiguous detection in the 360° full phase range.

[0062] Implementation Method 3: Implementation of a Symmetric Phase Detector (PD) The symmetrical phase detector adopts a differential symmetrical topology, consisting of a differential input stage, a current mirror load, and a differential output stage. The inductor-free design significantly reduces the chip area. The symmetrical structure of the circuit ensures that the phase detector has frequency-independent zero-crossing characteristics in the 18-23GHz frequency band. The input phase achieves fixed zero-crossing at -90°, and the output response accurately matches the ideal cosine function, providing a foundation for linear phase-to-voltage conversion.

[0063] Specific Implementation Method Four: Overall Circuit Technology and Parameter Implementation This invention is based on 40nm CMOS process fabrication, with a core circuit power supply voltage of 1.1V and a power consumption of only 22mW; the core area is only 0.016mm², and the inductor-free design further improves the integration density; the operating frequency covers the 18-23GHz RF millimeter wave band, achieving phase-voltage conversion in the 360° full phase range, with a linearity of 1.05% FSR, a root mean square error of 0.67% FSR, and a response settling time of approximately 120ns, which is more than 10 times faster than traditional solutions.

[0064] The beneficial effects of this invention: The radio frequency millimeter-wave phase-to-voltage converter proposed in this invention solves the core technical problems of traditional solutions through innovative architecture design including phase compression, linearized bias, three-state coupling network, and symmetrical phase detector, and has the following significant beneficial effects: No external clock dependency: The fully self-contained architecture requires no external reference clock or down-conversion clock, which improves the flexibility and integration of the circuit and makes it suitable for highly integrated RF millimeter-wave systems. 360° Full-Phase Unambiguous Detection: The Tri-State Coupled Network (TSCN) effectively solves the phase mode ambiguity problem of the frequency divider, achieving smooth and monotonic detection across the entire 360° phase range; High linearity: The combination of phase compression and linearized bias technology with a symmetrical phase detector achieves a high linearity of 1.05% FSR, with a root mean square error as low as 0.67% FSR and high phase detection accuracy. Low power consumption and small area: Implemented based on 40nm CMOS process, inductor-free design, core area is only 0.016mm², power consumption is only 22mW, which is 1 / 4 and 1 / 8 of the traditional analog phase detection solution, respectively, and the integration is greatly improved; Ultra-fast response: The response setup time is approximately 120ns, which is more than 10 times faster than traditional phase detection / conversion schemes. It can achieve dynamic phase tracking and is suitable for high-speed application scenarios such as fast frequency hopping phased arrays and adaptive equalization wired links. Wide bandwidth adaptability: The operating frequency covers the 18-23GHz RF millimeter wave band, and the maximum output voltage fluctuation under fixed phase is only 0.20% FSR, and the root mean square fluctuation is 0.09% FSR, with high performance stability within the frequency band.

[0065] The performance comparison between the present invention and existing RF millimeter-wave phase detection / conversion schemes is shown in the table below. The present invention achieves significant breakthroughs in core indicators such as no external clock, linearity, power consumption, area, and response speed, and its overall performance far exceeds that of existing schemes.

[0066] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A radio frequency millimeter-wave phase-to-voltage converter, characterized in that, include: The first frequency divider chain receives the first radio frequency millimeter wave input signal and is used to divide the signal to compress its phase. The second frequency divider chain receives the second radio frequency millimeter-wave input signal and is used to divide the signal to compress its phase. The first quadrature generator has its input connected to the output of the first frequency divider chain and is used to output the first 0° and 90° quadrature signals. The second quadrature generator has its input connected to the output of the second frequency divider chain and is used to output the second 0° and 90° quadrature signals. A three-state coupling network is connected between the first frequency divider chain and the second frequency divider chain to eliminate phase mode ambiguity generated by the first frequency divider chain and the second frequency divider chain during phase compression through reconfigurable coupled phase. A symmetrical phase detector has its first input terminal connected to the output terminal of the first quadrature generator and its second input terminal connected to the output terminal of the second quadrature generator, used to convert the phase difference of two quadrature signals into a voltage signal output.

2. The radio frequency millimeter-wave phase-to-voltage converter according to claim 1, characterized in that, The first and second frequency divider chains each include three cascaded CML latch structure frequency dividers. Each frequency divider outputs four orthogonal phases of 0°, 90°, 180°, and 270°. The three frequency dividers work together to achieve a phase compression ratio of N=8, compressing the input ±180° phase difference to ±22.5°.

3. The radio frequency millimeter-wave phase-to-voltage converter according to claim 2, characterized in that, The first and second quadrature generators utilize the inherent quadrature output of the last-stage frequency divider to provide a -90° linearized bias, so that the input phase of the symmetrical phase detector falls within the linear monotonic region [-112.5°, -67.5°] of the cosine response.

4. The radio frequency millimeter-wave phase-to-voltage converter according to claim 1, characterized in that, The tri-state coupling network includes three coupling channels: 0°, 90°, and -90°. The coupling capacitor is controlled by a MOSFET switch to switch the coupling phase θ between three states: 0°, θ>0°, and θ<0°, thereby eliminating phase mode ambiguity near ±180°.

5. The radio frequency millimeter-wave phase-to-voltage converter according to claim 4, characterized in that, The three-state coupling network is connected after the first-stage frequency divider, and a fixed 0° coupling network is connected between the second-stage and third-stage frequency dividers. This reduces the uncertainty of the phase mode from 8 to 2, and together with the three-state coupling network, it enables unambiguous detection across the entire 360° phase range.

6. The radio frequency millimeter-wave phase-to-voltage converter according to claim 1, characterized in that, The symmetrical phase detector adopts a differential symmetrical topology structure, consisting of a differential input stage, a current mirror load, and a differential output stage. It has an inductor-free design and features a frequency-independent -90° fixed zero-crossing characteristic in the 18-23GHz frequency band. Its output response matches an ideal cosine function.

7. The radio frequency millimeter-wave phase-to-voltage converter according to claim 1, characterized in that... The converter is implemented based on 40nm CMOS process, with a core circuit power supply voltage of 1.1V, power consumption of 22mW, core area of ​​0.016mm², response settling time of 120ns, operating frequency coverage of 18-23GHz, linearity of 1.05% FSR, and root mean square error of 0.67% FSR.

8. The radio frequency millimeter-wave phase-to-voltage converter according to claim 1, characterized in that, The converter requires no external clock and has an inductor-free design, featuring a fully self-contained architecture, and is compatible with RF millimeter-wave communication, phased array, millimeter-wave radar, and high-speed wired transmission systems.

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