Parallel polynomial gradient computation system and method based on cmos synapse transistor

By combining a parallel array architecture and voltage pulse programming in the floating substrate operation mode of CMOS neural synaptic transistors, high-precision polynomial gradient calculations were achieved, solving the process compatibility and reliability issues of memristor solutions, reducing production costs, and improving the manufacturability and computational efficiency of the system.

CN121981183BActive Publication Date: 2026-06-26SHENZHEN HOTCHIP TECH
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Patent Information

Application Number
CN202610439444.8
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2026-04-03
Publication Date
2026-06-26
Estimated Expiration
2046-04-03

AI Technical Summary

Technical Problem

In existing technologies, memristor solutions suffer from problems such as incompatibility between manufacturing processes and standard CMOS processes, low device yield, large differences between devices, state drift, and high power consumption, making it difficult to achieve high-precision parallel polynomial gradient calculations.

Method used

By employing CMOS synaptic transistors in floating substrate operation mode and combining them with a parallel array architecture, the conductivity state of the CMOS transistors is adjusted through a voltage pulse programming circuit to achieve dual-mode characteristics of neuronal and synaptic behavior. A neuromorphic computing system based on standard CMOS process is constructed. Utilizing mature CMOS process manufacturing technology, new materials such as memristors and back-end integration processes are avoided, resulting in a highly reliable, low-power, and easily integrated parallel polynomial gradient computing system. This solves the problems of poor process compatibility, low yield, and large device differences faced by memristor solutions, and achieves high-precision polynomial gradient calculation.

Benefits of technology

It achieves high-precision polynomial gradient calculation based on standard CMOS process, reduces production cost, improves system manufacturability and yield, overcomes device differences and state drift problems in memristor schemes, supports short-term and long-term flexibility, and shortens calculation time.

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Abstract

The application discloses a parallel polynomial gradient calculation system and method based on a CMOS nerve synapse transistor, and relates to the technical field of calculation systems.The parallel polynomial gradient calculation system based on the CMOS nerve synapse transistor adopts a basic calculation unit containing at least one CMOS transistor, and configures the CMOS transistor to exhibit the dual-mode characteristics of neuron behavior and synapse behavior in a floating substrate operation mode, and meanwhile, combines a parallel array architecture, so that the application realizes a neuromorphic calculation hardware based on a standard CMOS process, utilizes mature CMOS manufacturing technology, avoids special materials and post-integration processes required by emerging devices such as memristors, thereby improving the manufacturability and yield of the system, and reducing production costs.Meanwhile, the inherent device consistency and long-term stability of the CMOS transistor effectively overcome the problems of large differences between devices and state drift in the memristor scheme, and realize high-precision polynomial gradient calculation.
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