A copolymer organic plug-in finger structure reverser and a preparation method thereof

Abstract

The application discloses a kind of interpenetrating structure copolymer organic inverters and preparation method, including substrate, 2 organic field effect transistors, power supply end, ground terminal, output terminal, input terminal and interconnection line;Each organic field effect transistor includes organic semiconductor layer, photoetching dielectric barrier layer, source, drain and gate;Source includes n source fingers;Drain includes n drain fingers, n drain fingers and n source fingers equidistantly staggered, and form 2n-1 source-drain gap;Gate includes 2n-1 gate fingers arranged directly above source-drain gap.The application can effectively utilize photoetching dielectric barrier layer, introduce photoetching into the preparation of organic circuit, can effectively protect organic semiconductor material, and can be integrated on the same substrate Multiple organic field effect transistors are realized.In addition, interpenetrating structure can improve the on-current of circuit and reduce on-resistance, while the circuit opening voltage can be well reduced, and the power consumption of circuit is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit manufacturing, and particularly relates to a co-polymer organic inverter with a finger structure and a preparation method. BACKGROUND

[0002] Traditional integrated circuit manufacturing has many problems such as high energy consumption, high emission, high equipment dependence, high cost, and complex manufacturing process. With the new requirements of the country for low-carbon green development, co-polymer organic semiconductor materials have emerged as the times require. After nearly ten years of development, the advantages of low cost, high performance, high reliability, and low equipment dependence of organic semiconductor materials are well known, and co-polymer organic semiconductor devices and organic integrated circuits have been well developed.

[0003] However, organic semiconductors also have many disadvantages. Because most organic semiconductor materials use a solution spin coating process, they cannot be compatible with traditional photolithography. Photolithography requires the use of chemical reagents, but these reagents can erode the semiconductor layer and even the organic dielectric layer, causing the device to fail. The inability to use photolithography technology has resulted in a significant improvement in device performance and large device errors, making it difficult to achieve small-sized devices. This has hindered the development of organic field-effect transistors towards integration and diversification, and has limited the development of organic chips.

[0004] As is known, MOS tubes have a Miller effect. How to reduce the impact of the Miller effect on MOS tubes and make organic field-effect transistors compatible with photolithography technology remains to be solved. SUMMARY

[0005] The technical problem solved by the present application is to address the deficiencies of the prior art. The co-polymer organic inverter with a finger structure and the preparation method can effectively utilize photolithographic dielectric barrier and metal via technology, effectively introduce photolithographic technology into the preparation of organic circuits, effectively protect organic semiconductor materials, and enable the integration of multiple organic field-effect transistors on the same substrate. The organic field-effect transistors can be effectively interconnected, and the device structure designed as a finger structure can improve the on-current of the circuit and reduce the on-resistance, while also reducing the turn-on voltage of the circuit and reducing the power consumption of the circuit.

[0006] To solve the above technical problems, the technical solution adopted by the present application is as follows:

[0007] A co-polymer organic inverter with a finger structure includes a substrate, two organic field-effect transistors, a power supply terminal, a ground terminal, an output terminal, an input terminal, and an interconnection line.

[0008] Each organic field-effect transistor includes an organic semiconductor layer, a photolithographic dielectric barrier, a source, a drain, and a gate.

[0009] The organic semiconductor layer is made of an organic copolymer and is placed on top of the substrate.

[0010] The photolithography barrier layer is placed on top of the organic semiconductor layer.

[0011] The source electrode is embedded in an organic semiconductor layer, including source finger roots and a side of the source finger roots that are equidistantly and vertically arranged. n Each source pole finger joint; among them... n ≥2.

[0012] The drain includes drain finger roots and equidistant, vertically arranged electrodes on one side of the drain finger roots. n Each drain finger has a drain embedded in an organic semiconductor layer, and n Each leaky finger joint and n Each source pole finger is equidistantly and alternately inserted; n Each leaky finger joint and n Two source pole segments are formed between each 2 n -1 source-drain gap.

[0013] The gate is disposed on top of the photolithographic dielectric barrier layer, including the gate finger root and two gates equidistantly and vertically disposed on one side of the gate finger root. n -1 gate finger; 2 n -1 gate finger located at 2 n -1 directly above the source-drain gap, and the gate finger root is directly above the source finger root.

[0014] The two organic field-effect transistors are organic field-effect transistor one and organic field-effect transistor two.

[0015] The power supply terminal is connected to the drain of organic field-effect transistor one.

[0016] The ground terminal is connected to the source of organic field-effect transistor II.

[0017] The output terminal connects the source of organic field-effect transistor one and the drain of organic field-effect transistor two through an output interconnect.

[0018] The input terminals connect the gates of two organic field-effect transistors via gate interconnects.

[0019] The output interconnect and the gate interconnect together constitute the interconnect.

[0020] The power supply terminal includes an external power supply terminal, an internal power supply terminal, and a power supply through-hole; the internal power supply terminal is built into the left end of the organic semiconductor layer of the organic field-effect transistor; the external power supply terminal is located on top of the photolithography dielectric barrier layer directly above the internal power supply terminal; the power supply through-hole is arranged vertically and is used to electrically connect the external power supply terminal and the internal power supply terminal.

[0021] The grounding terminal includes an external grounding terminal, an internal grounding terminal, and a grounding through hole; the internal grounding terminal is built into the right end of the organic semiconductor layer of the organic field-effect transistor II; the external grounding terminal is located on the top of the photolithography dielectric barrier layer directly above the internal grounding terminal; the grounding through hole is arranged vertically and is used to electrically connect the external grounding terminal and the internal grounding terminal.

[0022] The output terminals include an external output terminal, an internal output terminal, and an output through-hole; the internal output terminal is embedded in the organic semiconductor layer between two organic field-effect transistors; the external output terminal is located on top of the photolithography dielectric barrier layer directly above the internal output terminal; the output through-hole is arranged vertically for electrically connecting the external output terminal and the internal output terminal.

[0023] Number of source and drain phalanges n The required output current of the copolymer organic inverter is determined based on the current required. The higher the required output current of the copolymer organic inverter, the better. n The larger the value.

[0024] n =4.

[0025] The height of both the source and drain electrodes is less than the thickness of the organic semiconductor layer, and the width of both the source and drain finger joints is 2 μm.

[0026] The gate also includes n -1 arc line; the arc line is used to connect the ends of two adjacent gate finger roots.

[0027] The dielectric constant K value of the photolithography barrier layer is not less than 3, and the material of the photolithography barrier layer is SiO2, Si3N4, Al2O3, phosphosilicate glass, borosilicate glass or semi-insulating polycrystalline silicon.

[0028] A method for preparing an interdigitated copolymer organic inverter includes the following steps.

[0029] Step 1: Evaporation of source and drain electrodes: Evaporate the built-in power supply terminal, built-in output terminal, and built-in ground terminal on the left, middle, and right ends of the top surface of the clean substrate, respectively; Evaporate the source and drain electrodes between the built-in power supply terminal and the built-in output terminal, and between the built-in output terminal and the built-in ground terminal, respectively; The source and drain electrodes between the built-in power supply terminal and the built-in output terminal are called the source and drain electrodes of organic field-effect transistor one; The source and drain electrodes between the built-in output terminal and the built-in ground terminal are called the source and drain electrodes of organic field-effect transistor two.

[0030] Source electrode, source electrode root, and one side of the source electrode root arranged at equal intervals and perpendicularly. n Each source pole finger joint; among them... n ≥2.

[0031] The drain includes drain finger roots and equidistant, vertically arranged electrodes on one side of the drain finger roots. n One leaky finger joint, n Each leaky finger joint and n Each source pole finger is equidistantly and alternately inserted; n Each leaky finger joint and n Two source pole segments are formed between each 2 n -1 source-drain gap.

[0032] The built-in power supply terminal is connected to the drain of organic field-effect transistor one.

[0033] The built-in ground terminal is connected to the source of organic field-effect transistor II.

[0034] The built-in output terminal connects the source of organic field-effect transistor one and the drain of organic field-effect transistor two through the output interconnect.

[0035] Step 2, Spin-coating organic semiconductor layer: Spin-coat an organic semiconductor layer onto the substrate, and embed the source, drain, built-in power supply terminal, built-in output terminal and built-in ground terminal in the organic semiconductor layer.

[0036] Step 3: Grow a photolithography barrier layer: Grow an inorganic photolithography barrier layer on top of the organic semiconductor layer.

[0037] Step 4: Evaporate metal through-holes, which specifically includes the following steps:

[0038] Step 4-1, Photolithography: Photoresist is spin-coated onto the top surface of the photolithography dielectric barrier layer directly above the built-in power supply terminal, built-in output terminal, and built-in ground terminal to form a photolithography mask.

[0039] Step 4-2: Forming through holes: Three vertical through holes are formed by gas etching, which respectively connect to the built-in power supply terminal, the built-in output terminal, and the built-in ground terminal.

[0040] Step 4-3, Metal Evaporation: Evaporate the same metal as the source or drain into the three through holes to form metal through holes; thus, the three metal through holes located directly above the built-in power supply terminal, built-in output terminal and built-in ground terminal are respectively formed as power supply through holes, output through holes and ground through holes.

[0041] Step 5: Evaporate the gate electrode, specifically:

[0042] External power supply terminal, external output terminal, and external grounding terminal are vapor-deposited on the top of the power supply through hole, output through hole, and grounding through hole, respectively.

[0043] A gate is deposited between the external power supply terminal and the external output terminal, and between the external output terminal and the external ground terminal; the gate includes gate fingers and two equidistant vertically arranged gate fingers on one side.n -1 gate finger; 2 n -1 gate finger located at 2 n -1 directly above the source-drain gap, and the gate finger root is directly above the source finger root.

[0044] Input terminals are deposited on the top surface of the photolithographic barrier layer outside the two gates, and the gate fingers of the two gates are connected through gate interconnects.

[0045] In step 1, the evaporation of the source, drain, built-in power supply, built-in output, and built-in ground terminals, as well as in step 5, the evaporation of the gate, all use photomasks, with the photoresist used being negative AZ5214; in step 4, the photoresist used in the metal via evaporation is positive S1813.

[0046] In step 3, the growth thickness of the photolithography dielectric barrier layer is 300 nm.

[0047] The present invention has the following beneficial effects:

[0048] 1. The photolithography dielectric barrier layer in this invention not only protects the semiconductor layer material from contamination and damage by organic solvents such as developer, NMP, and acetone during photolithography, but also significantly improves integration, repeatability, manufacturability, stability, and device performance. Furthermore, it has low equipment dependence, a simple manufacturing process, low cost, and high yield.

[0049] 2. The interdigitated structure in this invention can increase the circuit's on-current and reduce its on-resistance, while also significantly reducing the circuit's turn-on voltage and power consumption. This also reduces the intrinsic capacitance between the gate and drain, mitigating the Miller effect.

[0050] 3. The photolithography dielectric barrier layer and metal through-hole technology of the present invention effectively introduce photolithography technology into the fabrication of organic circuits, and this fabrication technology can realize the integration of multiple organic field-effect transistors on the same substrate, and the organic field-effect transistors can achieve effective interconnection. Attached Figure Description

[0051] Figure 1 A top view of a copolymer organic inverter with an interdigitated structure according to the present invention is shown.

[0052] Figure 2 The diagram shows a longitudinal cross-sectional view of a copolymer organic inverter with an interdigitated structure according to the present invention.

[0053] Figure 3 The diagram shows a top view of the source, drain, built-in power supply terminal, built-in ground terminal, and built-in output terminal of the present invention.

[0054] Figure 4A flowchart of a method for preparing an interdigitated copolymer organic inverter according to the present invention is shown.

[0055] Among them are:

[0056] 1. Substrate;

[0057] 2-1. Organic semiconductor layer; 2-2. Photolithography dielectric barrier layer;

[0058] 2-3. Source pole; 2-3a. Source pole phalanx; 2-3b. Source pole phalanx root;

[0059] 2-4. Drain electrode; 2-4a. Drain electrode knuckle; 2-4b. Drain electrode root;

[0060] 2-5. Gate; 2-5a. Gate finger; 2-5b. Gate finger root; 2-5c. Curved line;

[0061] 3-1. Built-in power supply terminal; 3-2. Power supply through hole; 3-3. External power supply terminal;

[0062] 4-1. Built-in grounding terminal; 4-2. Grounding through hole; 4-3. External grounding terminal;

[0063] 5-1. Built-in output terminal; 5-2. Output through hole; 5-3. External output terminal;

[0064] 6. Input terminal. Detailed Implementation

[0065] The present invention will now be described in further detail with reference to the accompanying drawings and specific preferred embodiments.

[0066] In the description of this invention, it should be understood that the terms "left side," "right side," "upper part," "lower part," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. "First," "second," etc., do not indicate the importance of the components, and therefore should not be construed as a limitation of this invention. The specific dimensions used in this embodiment are only for illustrating the technical solution and do not limit the scope of protection of this invention.

[0067] like Figure 1 , Figure 2 and Figure 3 As shown, a copolymer organic inverter with an interdigitated structure includes a substrate 1, two organic field-effect transistors, a power supply terminal, a ground terminal, an output terminal, an input terminal 6, and interconnects.

[0068] The substrate material is preferably any one of the following: glass substrate, flexible plastic, bulk silicon, silicon wafer, silicon carbide, gallium nitride, gallium arsenide, indium phosphide, and germanium silicon. In this embodiment, a glass substrate with a thickness of 0.5 mm is preferred.

[0069] The two organic field-effect transistors are organic field-effect transistor one and organic field-effect transistor two.

[0070] Each organic field-effect transistor includes an organic semiconductor layer 2-1, a photolithographic dielectric barrier layer 2-2, a source 2-3, a drain 2-4, and a gate 2-5.

[0071] An organic semiconductor layer is disposed on top of the substrate. Its material is an organic copolymer, preferably an organic compound such as pentacene, DPPT-TT, P3HT or naphthalimide-based N-type polymer, etc. In this embodiment, DPPT-TT dissolved in DCB is preferred.

[0072] A photolithographic dielectric barrier layer is disposed on top of the organic semiconductor layer. The dielectric constant K value of the photolithographic dielectric barrier layer is not less than 3, and is preferably SiO2, Si3N4, Al2O3, phosphosilicate glass, borosilicate glass, or semi-insulating polycrystalline silicon. In this embodiment, SiO2 is preferred, as SiO2 has a high dielectric constant, which improves the isolation performance between the gate and source of the device.

[0073] like Figure 3 As shown, the source is embedded in an organic semiconductor layer, including source finger roots 2-3b and a side of the source finger roots that are equidistantly and vertically arranged. n Each source pole finger 2-3a; among them n ≥2.

[0074] The drain electrode includes drain finger roots 2-4b and equidistantly vertically arranged on one side of the drain finger roots. n Each drain finger 2-4a has a drain embedded in an organic semiconductor layer, and n Each leaky finger joint and n Each source pole finger is equidistantly and alternately inserted; n Each leaky finger joint and n Two source pole segments are formed between each 2 n -1 source-drain gap.

[0075] Number of source and drain phalanges n The required output current of the copolymer organic inverter is determined based on the current required. The higher the required output current of the copolymer organic inverter, the better. n The larger the value, the better. In this embodiment, it is preferable to... n =4.

[0076] The height of both the source and drain electrodes is preferably less than the thickness of the organic semiconductor layer, and the width of both the source and drain electrodes is preferably 2 μm.

[0077] like Figure 1 As shown, the gate is disposed on top of the photolithographic dielectric barrier layer, including gate finger roots 2-5b and 2 gate fingers equidistantly and vertically disposed on one side of the gate finger roots. n -1 gate finger 2-5a, and n -1 arc line 2-5c; 2 n -1 gate finger located at 2 n -1 directly above the source-drain gap, and the gate finger root is directly above the source finger root.

[0078] The aforementioned arc-shaped line is used to connect the ends of two adjacent gate finger roots. In this embodiment, 2 n -1 gate finger and n -1 The arc-shaped line is preferably formed by an S-shaped bend of a single metal wire. The advantage of the arc-shaped line is that it can prevent the gate from undergoing electrical breakdown due to the gate metal and gate interconnect being too short as the input voltage increases. Therefore, the width and gate metal connection should be increased as much as possible without affecting the device performance. However, it is important to avoid covering the device drain terminal, otherwise it will increase the leakage current of the device, affecting the device performance and thus the overall inverter circuit performance.

[0079] The power supply terminal is connected to the drain of the organic field-effect transistor 1, and preferably includes a built-in power supply terminal 3-1, a power supply through-hole 3-2, and an external power supply terminal 3-3; the built-in power supply terminal is built into the left end of the organic semiconductor layer of the organic field-effect transistor 1; the external power supply terminal is located on the top of the photolithographic dielectric barrier layer directly above the built-in power supply terminal; the power supply through-hole is arranged vertically and is used to electrically connect the external power supply terminal and the built-in power supply terminal.

[0080] The grounding terminal is connected to the source of the second organic field-effect transistor, and preferably includes a built-in grounding terminal 4-1, a grounding through-hole 4-2, and an external grounding terminal 4-3. The built-in grounding terminal is built into the right end of the organic semiconductor layer of the second organic field-effect transistor. The external grounding terminal is located on the top of the photolithography dielectric barrier layer directly above the built-in grounding terminal. The grounding through-hole is arranged vertically and is used to electrically connect the external grounding terminal and the built-in grounding terminal.

[0081] The output terminal connects the source of organic field-effect transistor one and the drain of organic field-effect transistor two through an output interconnect. The output terminal preferably includes a built-in output terminal 5-1, an output via 5-2 and an external output terminal 5-3. The built-in output terminal is built into the organic semiconductor layer between the two organic field-effect transistors. The external output terminal is located on top of the photolithographic dielectric barrier layer directly above the built-in output terminal. The output via is arranged vertically and is used to electrically connect the external output terminal and the built-in output terminal.

[0082] The input terminals connect the gates of two organic field-effect transistors via gate interconnects.

[0083] The aforementioned output interconnects and gate interconnects together constitute the interconnects.

[0084] Furthermore, the source, drain, gate, power supply terminal, ground terminal, output terminal, input terminal, and interconnect are preferably any one of Ni, Cu, Ti, Ag, Au, Al, Pt, Pd, Ir, metal alloy, polycrystalline silicon, and graphite electrodes. In this embodiment, the source and drain metals are preferably Ni / Au, and the gate metal and metal via are both Cu.

[0085] like Figure 4 As shown, a method for preparing an interdigitated copolymer organic inverter includes the following steps.

[0086] Step 1: Evaporation of source and drain electrodes

[0087] Step 1-1: Clean the substrate: Sonicate the 0.5 mm thick glass substrate in acetone, alcohol and deionized water for 5 min each, then place it on a heating table and dry it at 100℃ for 10 min.

[0088] Steps 1-2: Evaporation of source and drain metal bodies

[0089] Built-in power supply terminal, built-in output terminal, and built-in ground terminal are deposited on the left, middle, and right ends of the top surface of a clean substrate, respectively. Source and drain terminals are deposited between the built-in power supply terminal and the built-in output terminal, and between the built-in output terminal and the built-in ground terminal, respectively. The source and drain terminals between the built-in power supply terminal and the built-in output terminal are called the source and drain terminals of organic field-effect transistor one. The source and drain terminals between the built-in output terminal and the built-in ground terminal are called the source and drain terminals of organic field-effect transistor two.

[0090] Source electrode, source electrode root, and one side of the source electrode root arranged at equal intervals and perpendicularly. n Each source pole finger joint; among them... n ≥2.

[0091] The drain includes drain finger roots and equidistant, vertically arranged electrodes on one side of the drain finger roots. n One leaky finger joint, n Each leaky finger joint and n Each source pole finger is equidistantly and alternately inserted; n Each leaky finger joint and n Two source pole segments are formed between each 2 n -1 source-drain gap.

[0092] The built-in power supply terminal is connected to the drain of organic field-effect transistor one.

[0093] The built-in ground terminal is connected to the source of organic field-effect transistor II.

[0094] The built-in output terminal connects the source of organic field-effect transistor one and the drain of organic field-effect transistor two through the output interconnect.

[0095] The evaporation of the source, drain, built-in power supply, built-in output and built-in ground terminals is carried out using a photomask, and the photoresist used is negative AZ5214.

[0096] In this embodiment, the specific evaporation method is as follows: Photoresist is spin-coated onto a cleaned glass substrate. After pre-baking, hard mode exposure with a photomask, post-baking, flood-E mode exposure without a photomask, and development, the substrate is placed in an evaporation machine to deposit 5nm and 45nm Ni metal. The evaporation rate does not exceed 1 Å / s, more preferably not exceeding 0.5 Å / s. In this embodiment, 5nm Ni metal is deposited at a rate of 0.1 Å / s, and 45nm Cu metal is deposited at a rate of 0.1 Å / s-0.5 Å / s. The evaporation rate determines the density of the deposited metal. Using a lower rate for the source / drain metal can improve the surface flatness of the metal, reduce the threshold voltage of the device, and improve performance. Alternatively, the source / drain metal body can be deposited using magnetron sputtering, which is also within the scope of this invention.

[0097] The spacing between the vapor-deposited source and drain electrodes (i.e., the source-drain gap) is the channel length of the device, and the number of drain and source fingers is... n The number of interdigits determines the output current of the device. The more interdigits there are, the larger the aspect ratio of the device, and the higher the output current will be. The interdigitation index is preferably 4. At the same time, the width of the source and drain metal should not be too wide, as this will increase the size of the overall circuit. If it is too narrow, it will also weaken the device's ability to withstand voltage. Therefore, in this embodiment, the drain and source interdigits are preferably 2μm wide. The height of the source and drain metal should not exceed the thickness of the semiconductor layer. If it does, the leakage current of the device will increase. If it is too thin, the conductive path of the device will be smaller, which will affect the transmission performance of the device.

[0098] Step 2, Spin-coating organic semiconductor layer: Spin-coat an organic semiconductor layer onto the substrate, and embed the source, drain, built-in power supply terminal, built-in output terminal and built-in ground terminal in the organic semiconductor layer.

[0099] The preferred spin-coating method is as follows: A 5 mg / ml DPPT-TT / DCB solution is dropped onto the surface, and the spin coater is operated according to the pre-set parameters (speed, acceleration, time). Then, it is heated at 80°C for 5 minutes, followed by annealing at 150°C for 1 hour. The operation of the spin coater according to the pre-set parameters is existing technology. Specifically, the spin coater operates at an acceleration of 200-800 rpm and 150-250 rpm / s for 8-13 seconds; at 1000-2000 rpm and 200-800 rpm / s for 40-100 seconds; and then decelerates to 0 rpm at an acceleration of -200 to -800 rpm for 2-8 seconds to spin coat the substrate surface.

[0100] The rotation speed of the spin coater determines the thickness of the semiconductor layer. The lower the rotation speed, the thicker the semiconductor layer. The thickness of the semiconductor layer determines the threshold voltage and output current of the device, which can effectively reduce the threshold voltage and increase the output current.

[0101] Step 3: Grow a photolithography barrier layer: Grow an inorganic photolithography barrier layer on top of the organic semiconductor layer.

[0102] A dielectric layer of not less than 200 nm is formed on top of the semiconductor layer. The preferred growth method is as follows: the substrate with the source and drain electrodes deposited is placed in a room temperature PECVD instrument, the vacuum degree is evacuated to below 3 mTorr, and then SiH4 gas is first introduced for 252 s, followed by N2O gas for 312 s, and the thickness of the dielectric layer 6 is controlled to be 300 nm.

[0103] The thickness of the aforementioned photolithographic dielectric barrier layer determines the gate control performance of the device. A thicker dielectric layer will result in weaker gate control, while a thinner layer will result in increased leakage current. This step is preferably 300nm.

[0104] Step 4: Evaporate metal through-holes, which specifically includes the following steps:

[0105] Step 4-1, Photolithography: Photoresist is spin-coated onto the top surface of the photolithography dielectric barrier layer directly above the built-in power supply terminal, built-in output terminal, and built-in ground terminal to form a photolithography mask.

[0106] Step 4-2: Forming through holes: Three 350nm vertical through holes are formed by gas O2 etching, which are respectively connected to the built-in power supply terminal, the built-in output terminal, and the built-in ground terminal.

[0107] Step 4-3, Metal Evaporation: Evaporate the same metal as the source or drain into the three through holes to form metal through holes; thus, the three metal through holes located directly above the built-in power supply terminal, built-in output terminal and built-in ground terminal are respectively formed as power supply through holes, output through holes and ground through holes.

[0108] The preferred method for depositing the aforementioned metal through-holes is as follows: the substrate with the etched vertical through-holes is placed in an electron beam evaporation apparatus, and the evaporation rate of the metal Cu is controlled to be no more than 0.4 Å / s, more preferably no more than 0.1 Å / s, and in this embodiment, it is 0.1 Å / s, with a deposited film thickness of 350 nm. Using a lower evaporation rate for the metal through-holes can reduce defects and improve connectivity.

[0109] Furthermore, the cross-sectional width of the metal through hole is preferably no more than the cross-sectional width of the external power supply terminal, external output terminal, or external grounding terminal.

[0110] In step 4, the same photoresist, S1813 (positive photoresist), is used for both etching and metal evaporation. Since etching is required, the positive photoresist offers higher resolution, resulting in higher etching precision. Furthermore, Flood-E mode exposure is unnecessary. After pre-baking, hard mode exposure with a photomask, post-baking, and development, the substrate can be placed into the etching machine.

[0111] Step 5: Evaporate the gate electrode, specifically:

[0112] External power supply terminal, external output terminal, and external grounding terminal are vapor-deposited on the top of the power supply through hole, output through hole, and grounding through hole, respectively.

[0113] A gate is deposited between the external power supply terminal and the external output terminal, and between the external output terminal and the external ground terminal; the gate includes gate fingers and two equidistant vertically arranged gate fingers on one side. n -1 gate finger; 2 n -1 gate finger located at 2 n -1 directly above the source-drain gap, and the gate finger root is directly above the source finger root.

[0114] For the evaporation of the aforementioned gate, the preferred photolithography method is negative photoresist AZ5214.

[0115] Input terminals are deposited on the top surface of the photolithographic barrier layer outside the two gates, and the gate fingers of the two gates are connected through gate interconnects.

[0116] The evaporation rates of the external power supply terminal, external ground terminal, external output terminal, input terminal, and gate interconnect are all no more than 1 Å / s, preferably no more than 0.5 Å / s. In this embodiment, three layers are deposited: first, a 5 nm layer of Cu is deposited at a rate of 0.1 Å / s; then, a 40 nm layer of Cu is deposited at a rate of 0.5 Å / s; and finally, a 5 nm layer of Cu is deposited at a rate of 0.1 Å / s. This evaporation method improves the density of the gate surface and the contact with the photoresist barrier layer, enhancing gate control and improving circuit performance.

[0117] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A copolymer organic inverter with an interdigitated structure, characterized in that: It includes a substrate, two organic field-effect transistors, a power supply terminal, a ground terminal, an output terminal, an input terminal, and interconnects; Each organic field-effect transistor includes an organic semiconductor layer, a photolithographic barrier layer, a source, a drain, and a gate; The organic semiconductor layer is made of an organic copolymer and is disposed on top of the substrate; A photolithography barrier layer is placed on top of the organic semiconductor layer; The source electrode is embedded in an organic semiconductor layer, including source finger roots and a side of the source finger roots that are equidistantly and vertically arranged. n One source pole finger joint; among them n ≥2; The drain includes drain finger roots and equidistant, vertically arranged electrodes on one side of the drain finger roots. n Each drain finger has a drain embedded in an organic semiconductor layer, and n Each leaky finger joint and n Each source pole finger is equidistantly and alternately inserted; n Each leaky finger joint and n Two source pole segments are formed between each 2 n -1 source-drain gap; The gate is disposed on top of the photolithographic dielectric barrier layer, including the gate finger root and two gates equidistantly and vertically disposed on one side of the gate finger root. n -1 gate finger; 2 n -1 gate finger located at 2 n -1 directly above the source-drain gap, and the gate finger root is directly above the source finger root; The two organic field-effect transistors are organic field-effect transistor one and organic field-effect transistor two; The power supply terminal is connected to the drain of organic field-effect transistor one; The ground terminal is connected to the source of organic field-effect transistor II; The output terminal connects the source of organic field-effect transistor one and the drain of organic field-effect transistor two through an output interconnect. The input terminals connect the gates of two organic field-effect transistors via gate interconnects; The output interconnect and the gate interconnect together constitute the interconnect.

2. The interdigitated copolymer organic inverter according to claim 1, characterized in that: The power supply terminal includes an external power supply terminal, an internal power supply terminal, and a power supply through-hole; the internal power supply terminal is built into the left end of the organic semiconductor layer of the organic field-effect transistor; the external power supply terminal is located on top of the photolithography dielectric barrier layer directly above the internal power supply terminal; the power supply through-hole is arranged vertically and is used to electrically connect the external power supply terminal and the internal power supply terminal. The grounding terminal includes an external grounding terminal, an internal grounding terminal, and a grounding through hole; the internal grounding terminal is built into the right end of the organic semiconductor layer of the organic field-effect transistor II; the external grounding terminal is located on the top of the photolithography dielectric barrier layer directly above the internal grounding terminal; the grounding through hole is arranged vertically and is used to electrically connect the external grounding terminal and the internal grounding terminal. The output terminals include an external output terminal, an internal output terminal, and an output through-hole; the internal output terminal is embedded in the organic semiconductor layer between two organic field-effect transistors; the external output terminal is located on top of the photolithography dielectric barrier layer directly above the internal output terminal; the output through-hole is arranged vertically for electrically connecting the external output terminal and the internal output terminal.

3. The copolymer organic inverter with interdigitated structure according to claim 1, characterized in that: Number of source and drain phalanges n The required output current of the copolymer organic inverter is determined based on the current required by the inverter. The higher the required output current, the better. n The larger the value.

4. The interdigitated copolymer organic inverter according to claim 3, characterized in that: n =4。 5. The interdigitated copolymer organic inverter according to claim 1, characterized in that: The height of both the source and drain electrodes is less than the thickness of the organic semiconductor layer, and the width of both the source and drain finger joints is 2 μm.

6. The interdigitated copolymer organic inverter according to claim 1, characterized in that: The gate also includes n -1 arc line; the arc line is used to connect the ends of two adjacent gate finger roots.

7. The interdigitated copolymer organic inverter according to claim 1, characterized in that: The dielectric constant K value of the photolithography barrier layer is not less than 3, and the material of the photolithography barrier layer is SiO2, Si3N4, Al2O3, phosphosilicate glass, borosilicate glass or semi-insulating polycrystalline silicon.

8. A method for preparing an interdigitated copolymer organic inverter, characterized in that: Includes the following steps: Step 1: Evaporation of source and drain electrodes: Evaporate the built-in power supply terminal, built-in output terminal, and built-in ground terminal on the left, middle, and right ends of the top surface of the clean substrate, respectively; Evaporate the source and drain electrodes between the built-in power supply terminal and the built-in output terminal, and between the built-in output terminal and the built-in ground terminal, respectively; The source and drain electrodes between the built-in power supply terminal and the built-in output terminal are called the source and drain electrodes of organic field-effect transistor one; The source and drain electrodes between the built-in output terminal and the built-in ground terminal are called the source and drain electrodes of organic field-effect transistor two. Source electrode, source electrode root, and one side of the source electrode root arranged at equal intervals and perpendicularly. n One source pole finger joint; among them n ≥2; The drain includes drain finger roots and equidistant, vertically arranged electrodes on one side of the drain finger roots. n One leaky finger joint, n Each leaky finger joint and n Each source pole finger is equidistantly and alternately inserted; n Each leaky finger joint and n Two source pole segments are formed between each 2 n -1 source-drain gap; The built-in power supply terminal is connected to the drain of organic field-effect transistor one; The built-in ground terminal is connected to the source of organic field-effect transistor II; The built-in output terminal connects the source of organic field-effect transistor one and the drain of organic field-effect transistor two through the output interconnect. Step 2, Spin-coating organic semiconductor layer: Spin-coat an organic semiconductor layer on the substrate, and embed the source, drain, built-in power supply terminal, built-in output terminal and built-in ground terminal in the organic semiconductor layer; Step 3: Growth of photolithography barrier layer: An inorganic photolithography barrier layer is grown on the top surface of the organic semiconductor layer; Step 4: Deposit metal through-holes, which specifically includes the following steps: Step 4-1, Photolithography: Photoresist is spin-coated onto the top surface of the photolithographic dielectric barrier layer directly above the built-in power supply terminal, built-in output terminal, and built-in ground terminal to form a photolithographic mask. Step 4-2: Forming through holes: Three vertical through holes are formed by gas etching, which respectively connect to the built-in power supply terminal, the built-in output terminal, and the built-in ground terminal; Step 4-3, Metal Evaporation: Evaporate the same metal as the source or drain into the three through holes to form metal through holes; thus, the three metal through holes located directly above the built-in power terminal, built-in output terminal and built-in ground terminal are respectively formed as power through holes, output through holes and ground through holes. Step 5: Evaporate the gate electrode, specifically: External power supply terminal, external output terminal, and external grounding terminal are vapor-deposited on the top of the power supply through hole, output through hole, and grounding through hole, respectively. A gate is deposited between the external power supply terminal and the external output terminal, and between the external output terminal and the external ground terminal; the gate includes gate fingers and two equidistant vertically arranged gate fingers on one side. n -1 gate finger; 2 n -1 gate finger located at 2 n -1 directly above the source-drain gap, and the gate finger root is directly above the source finger root; Input terminals are deposited on the top surface of the photolithographic barrier layer outside the two gates, and the gate fingers of the two gates are connected through gate interconnects.

9. The method for preparing the interdigitated copolymer organic inverter according to claim 8, characterized in that: In step 1, the evaporation of the source, drain, built-in power supply, built-in output, and built-in ground terminals, as well as in step 5, the evaporation of the gate, all use photomasks, with the photoresist used being negative AZ5214; in step 4, the photoresist used in the metal via evaporation is positive S1813.

10. The method for preparing the interdigitated copolymer organic inverter according to claim 8, characterized in that: In step 3, the growth thickness of the photolithography dielectric barrier layer is 300 nm.

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