Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device

a semiconductor device and information deletion technology, applied in the direction of semiconductor devices, radiocontrolled devices, electrical devices, etc., can solve the problems of difficult photolithography process patterned polysilicon films, inability to meet one of the important requirements, and number of processes, so as to achieve easy and proper formation and increase process margin

a semiconductor device and information deletion technology, applied in the direction of semiconductor devices, radiocontrolled devices, electrical devices, etc., can solve the problems of difficult photolithography process patterned polysilicon films, inability to meet one of the important requirements, and number of processes, so as to achieve easy and proper formation and increase process margin

US20050242377A1Inactive Publication Date: 2005-11-03UNITED MICROELECTRONICS CORP

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  • Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device
  • Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device
  • Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device

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Experimental program
Comparison scheme
Effect test

first embodiment

[0113] The first embodiment will be described first. In the first embodiment, an example in which the present invention is applied to a MOS transistor will be described. In the first embodiment, the structure of the MOS transistor and a manufacturing method therefore will be described together. FIGS. 1A to 1J are schematic sectional views showing steps in manufacturing the MOS transistor.

[0114] An element isolation structure is formed in an element isolation region on a p-type silicon semiconductor substrate by a so-called field shield element isolation method, thereby demarcating an element formation region.

[0115] More specifically, as shown in FIG. 1A, a silicon oxide film 2, a polysilicon film 3, and a silicon oxide film 4 are formed on a p-type silicon semiconductor substrate 1 to thicknesses of, e.g., about 50 nm, 200 nm, and 200 nm, respectively. A silicon nitride film 316 having a thickness of about 200 nm may be formed on the entire surface of the silicon oxide film 4 by C...

second embodiment

[0128] The second embodiment will be described next. As in the first embodiment, the structure of a MOS transistor and a manufacturing method therefore will be described together. The second embodiment is slightly different in the surface polishing method. A detailed description of the same steps as in the first embodiment will be omitted. The same reference numerals as in the first embodiment denote the same constituent elements in the second embodiment, and a detailed description thereof will be omitted.

[0129] In the second embodiment, in steps shown in FIGS. 1E and 1F of the above-described first embodiment, to easily and properly control polishing of a polysilicon film 24, silicon oxide films 4 serving as cap insulating films of field shield element isolation structures 22 are used as stoppers. When the cap insulating film is formed as an multilayered insulating film consisting of the silicon oxide film 4 and a silicon nitride film 316, the silicon nitride film 316 is used as a...

third embodiment

[0141] The third embodiment of the present invention will be described below. In the third embodiment, an example in which a semiconductor device according to the present invention and a manufacturing method therefore are applied to a MOS transistor will be described, as in the first embodiment. In the third embodiment, the structure of the MOS transistor and steps in manufacturing the MOS transistor will be described together. FIGS. 4A to 4G are schematic sectional views showing steps in manufacturing the MOS transistor of the third embodiment.

[0142] First, p- and n-type wells are formed in the surface region of a p-type silicon semiconductor substrate.

[0143] More specifically, as shown in FIG. 4A, the entire surface of a p-type silicon semiconductor substrate 41 is subjected to thermal oxidation to form a silicon oxide film (so-called preoxide film) 42 having a thickness of about 1,000 to 5,000 â„«. A resist 43 is applied to the surface of the silicon oxide film 42. The resist 43 ...

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Abstract

A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOGOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers is polished by chemical mechanical polishing (CMP) using the cap insulating films of the gate electrode wiring layers as stoppers, thereby forming the gate electrode wiring layers into separated patterns. With this arrangement, even when the width of the gate electrode wiring layer is reduced to the exposure limit in photolithography, the pad polysilicon film can be separated and patterned.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This Application is a Division of application Ser. No. 10 / 630,833 filed on Jul. 31, 2003. Application Ser. No. 10 / 630,833 is a Division of application Ser. No. 09 / 379,802 filed on Aug. 24, 1999. Application Ser. No. 09 / 379,802 is a Division of application Ser. No. 08 / 864,796 filed on May 28, 1997. Application Ser. No. 08 / 864,796 claims priority to Japanese Applications 8-156266 filed on May 28, 1996, 8-195437 filed on Jul. 5, 1996, 8-293369 filed on October 15, 9-19860 filed on Jan. 17, 1997, and 9-119884 filed on May 9, 1997, the contents of each of which are incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having a pad polysilicon film for extracting source and drain electrodes or a nonvolatile semiconductor memory such as an EEPROM and a me...

Claims

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Application Information

Patent Timeline
03 Nov 2005
Publication
US20050242377A1
IPC
H01L21/761; H01L21/765; H01L21/822; H01L21/8247; H01L27/06; H01L27/148; H10B69/00
CPC
H01L21/761; H01L21/765; H01L21/8221; H01L27/1463; H01L27/115; H01L27/11521; H01L27/11551; H01L27/0688
Inventors
EGUCHI, KOHEI; EGAWA, YUICHI