Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device

Abstract

A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOGOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers is polished by chemical mechanical polishing (CMP) using the cap insulating films of the gate electrode wiring layers as stoppers, thereby forming the gate electrode wiring layers into separated patterns. With this arrangement, even when the width of the gate electrode wiring layer is reduced to the exposure limit in photolithography, the pad polysilicon film can be separated and patterned.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This Application is a Division of application Ser. No. 10 / 630,833 filed on Jul. 31, 2003. Application Ser. No. 10 / 630,833 is a Division of application Ser. No. 09 / 379,802 filed on Aug. 24, 1999. Application Ser. No. 09 / 379,802 is a Division of application Ser. No. 08 / 864,796 filed on May 28, 1997. Application Ser. No. 08 / 864,796 claims priority to Japanese Applications 8-156266 filed on May 28, 1996, 8-195437 filed on Jul. 5, 1996, 8-293369 filed on October 15, 9-19860 filed on Jan. 17, 1997, and 9-119884 filed on May 9, 1997, the contents of each of which are incorporated herein by reference.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device having a pad polysilicon film for extracting source and drain electrodes or a nonvolatile semiconductor memory such as an EEPROM and a me...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor device and a method of manufacturing the same that can increase process margin without being affected by close location of element isolation structures or exposure limit. The method allows for the formation of a desired gate electrode or various wiring layers with a high degree of integration. The semiconductor device includes a transistor with a gate, source, and drain formed in an element active region demarcated by non-LOGOS insulating device isolation blocks on a semiconductor substrate. The upper surfaces of the gates and insulating films are planarized to the same level, and the method allows for the formation of non-LOGOS insulating device isolation blocks by burying a conductive film in a first insulating film and filling the space between adjacent ones of the non-LOGOS insulating device isolation blocks with a second insulating film. The semiconductor device can achieve high integration and micropatent text is provided.

Problems solved by technology

However, the following problems are posed in gate electrode formation.

In addition, this technique requires an extra polishing process to the manufacturing processes and therefore cannot meet one of important requirements associated with manufacturing of the semiconductor device, i.e., reduction of the number of processes.

However, when the width of the gate electrode wiring layer is reduced to the exposure limit, the resist pattern used to separate the pad polysilicon films on the gate electrode has a width equal to or smaller than the exposure limit, so the pad polysilicon films are hard to be patterned by photolithography processes.

For this reason, conventionally, the width of the gate electrode wiring pattern cannot be reduced to the exposure limit, thus impeding micropatterning of a semiconductor device.

However, the cumbersome processes as described above are required to form the mask.

In this case, addition of the mask formation and removing processes largely increases the number of manufacturing processes, resulting in a serious problem.

Actually, the gate is formed across the element active region and the element isolation region, so this technique cannot sufficiently cope with this situation.

The technique disclosed in Japanese Patent Laid-Open No. 8-70120 can be applied to only a semiconductor device having an SOT structure and therefore cannot be used for wide application purposes.

In addition, the SOT structure does not allow use of gates of the same conductivity type.

Deep problems such as development of so called bird's beak and penetration of field oxide into the element active region of the device occur in the process of the U.S. Pat. No. 5,422,289, in which an element isolation structure is constructed by a field oxide film formed by LOGOS process.

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