Memory with memory cells that include a MIM type capacitor with a lower electrode made for reduced resistance at an interface with a metal film

Abstract

A semiconductor device includes memory cells each having an MISFET for memory selection formed on one major surface of a semiconductor substrate and a capacitive element comprised of a lower electrode electrically connected at a bottom portion to one of a source and drain of the MISFET for memory selection via a first metal layer and an upper electrode formed on the lower electrode via a capacitive insulating film. The lower electrode has a thickness of 30 nm or greater at the bottom portion thereof. Sputtering with a high ionization ratio and high directivity, such as PCM, is adapted to the formation of the lower electrode to make only the bottom portion of a capacitor thicker.

Description

[0001] This is a divisional of application Ser. No. 10 / 777,704 filed Feb. 13, 2004. [0002] The entire disclosure of the prior application, application Ser. No. 10 / 777,704 is hereby incorporated by reference. [0003] This application claims priority to prior application JP 2003-36459, the disclosure of which is incorporated herein by reference.BACKGROUND OF THE INVENTION [0004] (1) Field of the Invention [0005] The present invention relates to a semiconductor device and a fabrication method therefor, and, more particularly, to an MIM (Metal Insulator Metal) type capacitor and a fabrication method therefor. [0006] (2) Description of the Related Art [0007] Each of memory cells of a DRAM (Dynamic Random Access Memory) comprises a selection transistor and a capacitor. As the micropatterning of memory cells becomes finer with the advancement of the microfabrication technology, the amount of electric charges stored in a capacitor undesirably becomes smaller. To solve this problem, active st...

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Benefits of technology

[0016] It is therefore an object of the present invention to provide an MIM type capacitor in which a lower electrode is made thick only at its bottom portion and which is capable of reducing the number of fabrication processes and securing the alignment margin, and a fabrication method for the capacitor.

[0018] It is a further object of the invention to provide an MIM type capacitor which reduces the resistance at the interface between its lower electrode and barrier metal film by increasing the process margin for layer alignment, and a fabrication method for the capacitor.

[0036] The invention provides an MIM type capacitor whose lower electrode is made thick only at its bottom portion without increasing the number of fabrication processes and reducing the process margin for layer alignment. The interface between the lower electrode and barrier metal film of the acquired MIM type capacitor is not oxidized and the capacitor has a small leak current and a low conductive resistance.

[0037] The invention is further characterized in the structure where a second barrier metal film of the same material as the first barrier metal film is laminated on the bottom portion of the lower electrode. The invention can therefore reduce the resistance at the interface between the lower electrode and barrier metal film by increasing the process margin for layer alignment.

Problems solved by technology

As the micropatterning of memory cells becomes finer with the advancement of the microfabrication technology, the amount of electric charges stored in a capacitor undesirably becomes smaller.

Further, the volume expansion that also occurs due to the formation of the titanium oxide film brings about a problem of applying stress to the capacitor, thereby increasing the leak current of the capacitor.

However, increasing the thickness of the lower electrode by CVD normally causes a film of the same thickness to grow on the side wall portion and the bottom portion.

However, the prior art illustrated in FIG. 4 has a problem that forming only the bottom portion of the hole in a step separate from the formation of the capacitor portion increases the number of required steps.

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