442 results about "Step height" patented technology

A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source/drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.

An interferometer and ellipsometer are combined in a metrology tool to measure the step height of a sample, which may include transparent layers. The metrology tool includes a shared light source that provides a light beam for an interferometer and a light beam for an ellipsometer, interferometer optics which direct the light beam for an interferometer to reflect off of a sample and ellipsometer optics which direct the light beam for an ellipsometer to reflect off a sample, and a detector element for receiving both the reflected light beam for an interferometer and the light beam for an ellipsometer. The light source may produce a single beam that is split into an interferometer and an ellipsometer beam with a beam splitter. In another embodiment, the interferometer and ellipsometer may share at least one of a polarizer, analyzer, or detector element.

A method for fabricating metal gate transistors and a polysilicon resistor is disclosed. First, a substrate having a transistor region and a resistor region is provided. A polysilicon layer is then formed on the substrate to cover the transistor region and the resistor region of the substrate. Next, a portion of the polysilicon layer disposed in the resistor is removed, and the remaining polysilicon layer is patterned to create a step height between the surface of the polysilicon layer disposed in the transistor region and the surface of the polysilicon layer disposed in the resistor region.

The present invention provides an oxide CMP slurry composition for use in planarizing silicon oxide-containing films via CMP during CMOS device fabrication, and a method of planarizing silicon oxide-containing films via CMP using the slurry composition. The oxide CMP slurry composition according to the invention includes: (i) proline, lysine and/or arginine; (ii) a pyrrolidone compound; and (iii) abrasive particles. Proline is presently most preferred for use in the invention. In the STI sub-process of the CMOS device fabrication process, the oxide CMP slurry composition according to the present invention acts to aggressively remove only the silicon dioxide overburden on the processed wafer that is in contact with a polishing pad, which results in the formation of a substantially planar, defect-free surface. The oxide CMP slurry composition according to the invention does not aggressively remove trench silicon dioxide thereby allowing for extended polishing beyond the end point without substantially increasing the minimum step height.

The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region.

Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface. The method further comprises at least partially filling the recessed region with a III-V compound semiconductor material overlaying the surface.

The invention provides a modulation method of a modular multilevel converter (MMC). The modulation method comprises the following steps: calculating a reference voltage of each submodule according to the reference voltage of each bridge arm, current direction of buffer inductance of each bridge arm and capacitive voltage of each submodule; and comparing the reference voltage of each submodule with the same triangular carrier so as to decide the on-off state in each submodule and realize pulse width modulation (PWM). The modulation method has the beneficial effects that output voltage of the MMC can generate 2N+1 (N is the number of the submodules of the upper bridge arm or the lower bridge arm in the MMC) electrical levels without carrier phase shifting (CPS), thus simplifying implementation procedures and saving software and hardware resources; the step height of a step wave of the output voltage is only 50% of that of each capacitive voltage, thus obviously reducing the harmonic content of the output voltage; the capacitive voltage on each submodule can be balanced without any capacitive voltage closed-loop controller; and meanwhile the average voltage on the buffer inductance of each bridge arm is zero without a direct current (DC) component and a low frequency component, thus reducing volume and weight of the inductance.

A method for fabricating DRAM cells according to the present invention includes the steps of: forming a trench within a semiconductor substrate using a stacked layer as a mask, said stacked layer composed of a silicon oxide film and a silicon nitride film formed in an active region of said semiconductor substrate; forming a first insulation layer on a bottom and sides of said trench; depositing a first conductive layer on whole surface of said semiconductor substrate including said trench; etching back said conductive layer to be recessed from a top surface of said semiconductor substrate and forming bit lines of said first conductive layer on said bottom of said trench in a direction of column; filling a second insulation layer in said trench; removing said stacked layer and a part of said second insulation layer to expose said semiconductor substrate in said active region and planarizing said semiconductor substrate simultaneously; forming a gate insulation layer on said semiconductor substrate;forming a gate structure of a second conductive layer on said gate insulation layer; forming a spacer of an insulation layer on said sides of said gate structure of said second conductive layer; forming source and drain regions on both sides of said gate structure of said second conductive layer;forming a third insulation layer on said semiconductor substrate; connecting said bit lines to a first one of said source and drain regions with a plug of a third conductive layer filled in a contact hole inside said third insulation layer and said second insulation layer; forming a storage node electrode connected to a second one of said source and drain regions; andforming a plate electrode overlying a dielectric layer disposed said storage node electrode.Accordingly, the present invention has the buried bit lines in the trench, making it easy to secure a process margin in the subsequent process, maintaining a constant width of the bit lines to lower the resistance thereof. Furthermore, the bit lines disposed under the word lines has an advantage over patterning the node contact due to the low step height, with enhanced capacitance of the capacitor.

Methods are disclosed that provide for structures and techniques for the fabrication of ordered arrangements of crystallographically determined nanometer scale steps on single crystal substrates, particularly SiC. The ordered nanometer scale step structures are produced on the top surfaces of mesas by a combination of growth and etching processes. These structures, sometimes referred to herein as artifacts, are to enable step-height calibration, particularly suitable for scanning probe microscopes and profilometers, from less than one nanometer (nm) to greater than 10 nm, with substantially no atomic scale roughness of the plateaus on either side of each step.

Multi-mode diode emitters are stacked in a staircase formation to provide a spatially-mulitplexed output. Improved coupling efficiency is achieved by providing tilted collimated output beams that determine an effective step height of the stepped structure. Since the effective step height is dependent on the tilt angle, a variable number of emitters can be used inside packages having a same physical step height, while still attaining high coupling efficiency.

A step exercising system for an aerobic step workout is constructed as a portable inclined step ramp. The ramp is sloped towards a user such that the user can step up onto the ramp at various heights, thereby regulating the degree of intensity of the workout without having to suspend the workout to adjust the step height, as is the case when using a conventional aerobic step having a raised level platform.

A setting unit 33 configured to set a first landing permissible region in order to ground a free leg side foot 16 within an upper tread surface or a lower tread surface of a step existing ahead of a legged mobile robot 1 in a traveling direction, and a setting unit 34 configured to set a second landing permissible region in order to ground the free leg side foot 16 on an edge of the upper tread surface or the lower tread surface are provided to switch landing permissible regions for movement control of the robot 1 according to a step height.

The present invention relates to a polishing pad which is characterized in that it is of micro rubber A-type hardness at least 80°, has closed cells of average cell diameter no more than 1000 mum, is of density in the range 0.4 to 1.1 and contains polyurethane and polymer produced from a vinyl compound. When planarizing local unevenness on a semiconductor substrate with the polishing pad relating to the present invention, the polishing rate is high, the global step height is low, dishing does not readily occur at the metallic interconnects, clogging and permanent set of the surface layer region do not readily occur and the polishing rate is stable.

An organic light emitting display device and a method of fabricating the same. A dummy pattern is formed in an emission region to increase the step height of the emission region by an electrode material while a thin film transistor is fabricated, so that a distance between a pixel electrode and a donor film is decreased during fabrication of an organic layer. This reduced distance reduces laser energy for transfer using laser-induced thermal imaging, thus improving life span and efficiency of the device. Further, the pixel electrode can extend into a thin film transistor region and a capacitor region, thus enhancing an aperture ratio.

A method for processing a semiconductor substrate includes providing a substrate having at least one filter region with a plurality of bond pads in it. Metal is deposited above the bond pads, to reduce the bond pad step height. A planarization layer is formed such that the deposited metal has a height near to a height of the planarization layer. At least one color resist layer is formed above the planarization layer.

The utility model discloses an on-line measuring system for interference step height in composite wave from optical fiber raster. A composite optical fiber interferometer is built by making use of the Bragg wavelength reflective property in the optical fiber raster. The composite interferometer comprises two optical fiber Michelson interferometers with almost coincident light paths. A Michelson interferometer is used for measuring, and the other is used for stabilizing the system. The impact on the measuring system brought by the environmental interference is corrected through the feedback control compensation, so that the system is applicable to online measuring. Three lasers emit lights of slightly different wavelength but within 1550nm waveband. Because of the effects of the optical fiber raster reflecting Bragg wavelength and self-chirped optical fiber raster reflecting the specific spectrum, a wavelength acts on the stabilizing interferometer for stabilizing the measuring system, and the other two wavelengths act on the measuring interferometer to produce composite wave interference for actual measurement. Different composite wavelengths can be gained by regulating the two wavelengths acting on the measuring interferometer; and the measurement of different step heights can be carried out.

The invention relates to a nanometer multi-step height sample template and relative production/, wherein it transforms the thickness of film into the step height of said template, and controls its thickness to control the height of step, etches the step shape via dry and wet etching techniques to obtain the nanometer multi-step height sample template. Since the film preparation can realize Si3N4 film and Cr film at 10nm level, and the dry and wet etching techniques can etch multi-step shape, the invention can reduce the hardness of production, with low cost. The inventive product can be used to test and collect of scanning electric microscope, etc.

A transistor of a semiconductor memory device including a semiconductor substrate having a plurality of active regions and a device isolation region, a plurality of first and second trench device isolation layers, which are arranged alternately with each other on the device isolation region of the semiconductor substrate, the first trench device isolation layers having a first thickness corresponding to a relatively high step height, and the second trench device isolation layers having a second thickness corresponding to a relatively low step height, a recess region formed in each of the active regions by a predetermined depth to have a stepped profile at a boundary portion thereof, the recess region having a height higher than that of the second trench device isolation layers to have an upwardly protruded portion between adjacent two second trench device isolation layers, a gate insulation layer, and a plurality of gate stacks formed on the gate insulation layer to overlap with the stepped profile of the respective active regions and the protruded portion of the relevant recess region.

A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line.

As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.