Method for manufacturing semiconductor device having buried gate

Abstract

A method for manufacturing a semiconductor device having a buried gate is provided. A gate conductive layer is first formed in the peri region before a bit line contact is formed in the cell region, so that a fabrication process is simplified and the problem caused by a step height between the cell region and the core / peri region is not encountered.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device that simplifies the manufacturing process of a semiconductor device having a buried gate and minimizes problems caused by the manufacturing process. Background technique [0002] As the integration level of semiconductor storage devices such as Dynamic Random Access Memory (DRAM) increases, the area occupied by Metal Oxide Semiconductor (MOS) transistors gradually decreases. Accordingly, the channel length of the MOS transistor is also reduced, so that a short channel effect occurs. Specifically, if a short channel effect occurs in an access MOS transistor in a memory unit (cell, also called a unit cell) used for DRAM, the threshold voltage of the DRAM cell decreases, and the leakage current of the DRAM cell increases , so the refresh characteristics of the DRAM are degraded. [0003] Therefore,...

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Problems solved by technology

[0009] However, according to the prior art described above, a polysilicon portion for forming a bit line in the cell region and a portion of polysilicon for forming a gate in the core / peripheral region are excessively deposited near the boundary portion between the cell region and the core / peripheral region. another polysilicon portion of the pole, unexpectedly encountering various problems when removing the over-deposited polysilicon portion

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